tag: Universitat Politecnica de Catalunya

Workload-Specific Data Movements Across AI Workloads in Multi-Chiplet AI Accelerators
By Technical Paper Link - 04 Nov, 2024 - Comments: 0

A new technical paper titled "Communication Characterization of AI Workloads for Large-scale Multi-chiplet Accelerators" was published by researchers at Universitat Politecnica de Catalunya. Abstract "Next-generation artificial intelligence (AI) workloads are posing challenges of scalability and robustness in terms of execution time due to their intrinsic evolving data-intensive characteris... » read more

Chip Industry Technical Paper Roundup: Feb. 19
By Liz Allan - 19 Feb, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=199 /] More ReadingTechnical Paper Library home » read more

FPGA-Based HW/SW Platform For Pre-Silicon Emulation Of RISC-V Designs (Barcelona Supercomputing Center)
By Technical Paper Link - 15 Feb, 2024 - Comments: 0

A technical paper titled “Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs” was published by researchers at Barcelona Supercomputing Center and Universitat Politècnica de Catalunya. Abstract: "Emulating chip functionality before silicon production is crucial, especially with the increasing prevalence of RISC-V-based designs. FPGAs are promising candidate... » read more

Chip Industry Technical Paper Roundup: Feb. 6
By Liz Allan - 06 Feb, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=187 /] More ReadingTechnical Paper Library home » read more

Analysis Of Accel-Sim GPGPU Simulator And Model Improvements
By Technical Paper Link - 30 Jan, 2024 - Comments: 0

A technical paper titled “Analyzing and Improving Hardware Modeling of Accel-Sim” was published by researchers at Universitat Politècnica de Catalunya. Abstract: "GPU architectures have become popular for executing general-purpose programs. Their many-core architecture supports a large number of threads that run concurrently to hide the latency among dependent instructions. In modern GPU... » read more

Chip Industry’s Technical Paper Roundup: October 3
By Liz Allan - 03 Oct, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=150 /] Related Reading Technical Paper Library home » read more

Detecting Hardware Trojans Using Analytical Modeling
By Technical Paper Link - 27 Sep, 2023 - Comments: 0

A technical paper titled “Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models” was published by researchers at National University of Singapore and Universitat Politecnica de Catalunya. Abstract: "Hardware Trojans, malicious components that attempt to prevent a chip from operating as expected, are carefully crafted to circumvent detection during the pre-deploymen... » read more

Technical Paper Round-Up: June 28
By Linda Christensen - 28 Jun, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=35 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

OTA On-Chip Computing That Conquers A Bottleneck In Wired NoC Architectures
By Technical Paper Link - 21 Jun, 2022 - Comments: 0

New research paper titled "Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing" from researchers at IBM Research, Zurich Switzerland and Universitat Politecnica de Catalunya, Barcelona, Spain Abstract: "Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using very long random vectors (aka hyp... » read more

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