tag: University of California Santa Cruz

A Survey Of Recent Advances In Spiking Neural Networks From Algorithms To HW Acceleration
By Technical Paper Link - 13 Dec, 2023 - Comments: 0

A technical paper titled “Recent Advances in Scalable Energy-Efficient and Trustworthy Spiking Neural networks: from Algorithms to Technology” was published by researchers at Intel Labs, University of California Santa Cruz, University of Wisconsin-Madison, and University of Southern California. Abstract: "Neuromorphic computing and, in particular, spiking neural networks (SNNs) have becom... » read more

Chip Industry’s Technical Paper Roundup: August 9
By Liz Allan - 09 Aug, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=124 /] More Reading Technical Paper Library home » read more

Performance Enhancement Of An Si Photodetector By Incorporating Photon-Trapping Surface Structures
By Technical Paper Link - 02 Aug, 2023 - Comments: 0

A technical paper titled “Achieving higher photoabsorption than group III-V semiconductors in ultrafast thin silicon photodetectors with integrated photon-trapping surface structures” was published by researchers at University of California Davis, W&WSens Devices Inc., and University of California Santa Cruz. Abstract: "The photosensitivity of silicon is inherently very low in the vis... » read more

Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract "With technology scaling, the size of cache systems in chip-multiprocessors (CMPs) has been dramatically increased to efficiently store and manipulate a large amount of data in future applications and decrease the gap between cores and off-chip memory accesses. For future CMPs architecting, 3D stacking of LLCs has been recently introduced as a new methodology to combat to performance ... » read more

Power/Performance Bits: Feb. 26
By Jesse Allen - 26 Feb, 2019 - Comments: 0

Integrated RRAM for edge AI Researchers at CEA-Leti and Stanford University have developed the first circuit integrating multiple-bit non-volatile Resistive RAM (RRAM) with silicon computing units, as well as new memory resiliency features that provide 2.3-times the capacity of existing RRAM. The proof-of-concept chip monolithically integrates two heterogeneous technologies: 18KB of on-chip... » read more

Power/Performance Bits: Nov. 21
By Jesse Allen - 21 Nov, 2017 - Comments: 0

Greener greenhouses Researchers at the University of California, Santa Cruz are testing greenhouses capable of generating some of their own energy, without hampering plant growth. Greenhouses use electricity to control temperature and power fans, lights, and other monitoring systems. Electricity-generating solar greenhouses utilize Wavelength-Selective Photovoltaic Systems (WSPVs), a novel ... » read more

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