Chip Industry’s Technical Paper Roundup: August 9

CNN HW architecture; eGPU for FPGAs; superconducting diode effect; enhancing Si photodetectors; fully homomorphic encryption; band nesting effect in TMDs; safety island for HPC devices; analog circuits for SNNs.


New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation Samsung AI Center and University of Cambridge
eGPU: A 750 MHz Class Soft GPGPU for FPGA Intel Corporation and Imperial College London
Achieving higher photoabsorption than group III-V semiconductors in ultrafast thin silicon photodetectors with integrated photon-trapping surface structures University of California Davis, W&WSens Devices Inc., and University of California Santa Cruz
BASALISC: Programmable Hardware Accelerator for BGV Fully Homomorphic Encryption COSIC KU Leuven, Galois Inc., and Niobium Microsystems
Achieving near-perfect light absorption in atomically thin transition metal dichalcogenides through band nesting University of Minnesota, University of Notre Dame, and Korea Advanced Institute of Science and Technology (KAIST)
Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains Barcelona Supercomputing Center and Intel
Neuromorphic analog circuits for robust on-chip always-on learning in spiking neural networks University of Zurich and ETH Zurich
Ubiquitous Superconducting Diode Effect in Superconductor Thin Films Massachusetts Institute of Technology (MIT), IBM Research Europe, U.S. Army DEVCOM Army Research Laboratory, Centro de Física de Materiales (CFM-MPC), Hanford High School, Vestavia Hills High School, Donostia International Physics Center (DIPC), Condensed Matter Physics Center (IFIMAC), and Universidad Autónoma de Madrid

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