Chip Industry Technical Paper Roundup: Sept. 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=256 /] More ReadingTechnical Paper Library home » read more

Characterizing Three Supercomputers: Multi-GPU Interconnect Performance


A new technical paper titled "Exploring GPU-to-GPU Communication: Insights into Supercomputer Interconnects" was published by researchers at Sapienza University of Rome, University of Trento, Vrije Universiteit Amsterdam, ETH Zurich, CINECA, University of Antwerp, IBM Research Europe, HPE Cray, and NVIDIA. Abstract "Multi-GPU nodes are increasingly common in the rapidly evolving landscape... » read more

Chip Industry Week In Review


The University of Texas at Austin’s Texas Institute for Electronics (TIE) was awarded $840 million to establish a Department of Defense microelectronics manufacturing center. This center will focus on developing advanced semiconductor microsystems to enhance U.S. defense systems. The project is part of DARPA's NGMM Program. The U.S. Dept. of Commerce announced preliminary terms with Global... » read more

Power/Performance Bits: April 5


Wafer-scale graphene In an attempt to make graphene more useful for photonic devices, researchers from CNIT, Istituto Italiano di Tecnologia (IIT), Tecip Institute, University of Cambridge, and Graphene Flagship Associated Member and spin-off CamGraphIC developed a wafer-scale graphene fabrication technology that uses predetermined graphene single-crystal templates, allowing for integration in... » read more