tag: UPF

Best Practices For Power-Aware Verification: Because Designing For Low Power Is Only Half The Battle
By Chandu Challapalli - 15 May, 2025 - Comments: 0

As modern chips push the limits of power efficiency, power management has become a top priority. With today’s increasingly complex devices, verifying power intent isn’t just a technical requirement. It’s a necessity for building reliable silicon. One of the most important lessons learned in recent years is that RTL and power intent must evolve together. Treating power intent as a post... » read more

Controlling Leakage Power
By Matthew Hogan - 17 Feb, 2025 - Comments: 0

IC designers face a significant challenge in managing leakage power - a phenomenon that can profoundly impact your device's power, performance, area (PPA), and overall reliability. Leakage can occur in various ways, from parasitic leakage to analog gate leakage or digital gate leakage, and you must address these issues with great care, as even subtle circuit changes can lead to reliability prob... » read more

Power Issues Causing More Respins At 7nm And Below
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Power consumption has been a major design consideration for some time, but it is far from being a solved issue. In fact, an increasing number of designs have a plethora of power-related problems, and those problems are getting worse in new chip designs. Many designs today are power-limited — or perhaps more accurately stated, thermal-limited. A chip only can consume as much power as it is ... » read more

Power Domain Implementation Challenges Escalate
By Ann Mutschler - 20 Jun, 2022 - Comments: 0

The number power domains is rising as chip architects build finer-grained control into chips and systems, adding significantly to the complexity of the overall design effort. Different power domains are an essential ingredient in partitioning of different functions. This approach allows different chips in a package, and different blocks in an SoC, to continue running with just enough power t... » read more

The Challenges Of Incremental Verification
By Brian Bailey - 28 Apr, 2022 - Comments: 1

Verification consumes more time and resources than design, and yet little headway is being made to optimize it. The reasons are complex, and there are more questions than there are answers. For example, what is the minimum verification required to gain confidence in a design change? How can you minimize the cost of finding out that the change was bad, or that it had unintended consequences? ... » read more

Power-Aware Test: Addressing Power Challenges In DFT And Test
By Rahul Singhal - 10 Aug, 2021 - Comments: 0

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design sizes increase, the total power consumption of the chip also increases. While process node scaling reduces a transistor’s size and its operating-voltage, power scaling has not kept up with the si... » read more

Lower Power Chips: What To Watch Out For
By Ann Mutschler - 08 Jul, 2021 - Comments: 0

Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context of other issues. With each new leading-edge process node, and with increasingly dense packaging, the potential for problematic interactions is growing. That, in turn, can lead to poor yield, cos... » read more

Primary, Anonymous, or What?
By Siemens EDA - 09 Jun, 2021 - Comments: 0

Top level primary I/Os remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications are multifold for RTL and gate level simulations of them. This paper studies the “simulation-impacting” features of design top IOs and the effect of each feature on v... » read more

The Many Flavors Of UPF: Which Is Right For Your Design?
By Madhur Bhargava - 11 Feb, 2021 - Comments: 0

Energy efficient electronic systems require sophisticated power management architectures that present difficult low-power verification challenges. Accellera introduced the Unified Power Format (UPF) standard in 2007 to help engineers deal with these complex issues. To keep pace with the growing complexity of low-power designs, the UPF standard has itself continued to evolve through the relea... » read more

Customizing Low-Power Platforms Using UPF Dynamic Properties
By Progyna Khondkar - 12 Nov, 2020 - Comments: 0

Low power design and verification engineers need a way to continuously probe various dynamic properties of UPF objects in order to monitor the current state of a verification strategy and utilize that information to develop custom low-power verification environments. Unfortunately, there hasn’t been a reliable, formalized way to do this. Since availability of the dynamic properties of unif... » read more

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