tag: UPF

Energy Boost For Power Standards
By Brian Bailey - 09 Oct, 2014 - Comments: 0

If the amount of standards work and industry effort that is being expended on a given topic is any indicator of the growing importance of a design concern, then power has most certainly become the hottest topic in the industry. Thankfully, it seems as if everyone has learned their lessons from the CPF/[gettech id="31044" t_name="UPF"] struggles and is attempting to coordinate activities, while ... » read more

Interpreting UPF For A Mixed-Signal Design Under Test
By Mentor, a Siemens Business - 23 Jul, 2014 - Comments: 0

This paper describes a methodology (as implemented in the Mentor Graphics Questa ADMS mixed-signal simulator) for interpreting the Unified Power Format (UPF) for analog mixed-signal designs coded in Verilog-AMS, VHDL-AMS, or SPICE. No changes to the UPF syntax or file are required. A complete implementation and a demonstration of its use in a sample case are provided as proof of concept. To ... » read more

S-L Power Modeling Gains Steam
By Ann Mutschler - 12 Jun, 2014 - Comments: 1

Power analysis, architectural exploration and optimization of an SoC is a hot topic of discussion today. It is well accepted this must be addressed at a higher level of abstraction because not just the hardware must be taken into account with power intent and power management structures. It has to be viewed from a system point of view, as well, where the hardware resides along with the opera... » read more

Reduced Power To The People!
By Steve Schulz - 29 May, 2014 - Comments: 0

Fifteen years ago, many of us involved in writing the design chapter of the ITRS (International Technology Roadmap for Semiconductors) already knew that power/energy consumption eventually would become a major problem for the industry’s growth. Engineers developing microprocessors (CPUs and DSPs) and graphics engines (GPUs) led the wave of predictions, because extrapolating known trend data s... » read more

Localized, System-Level Protocol Checks And Coverage Closure
By Various Writers - 23 Apr, 2014 - Comments: 0

Broadcom recently developed a unified, scalable, verification methodology based on the Veloce emulation platform. In order to test this new environment, they ran a test case, which proved that they can take assertions, compile them into Veloce, and verify that they fire accurately. In so doing, they were able to provide proof of concept for their primary goal: the creation of an internal flow t... » read more

Know What To Look For
By Ann Mutschler - 13 Mar, 2014 - Comments: 0

With the number of power domains exploding in today’s ICs, it’s extremely difficult to include all different modes of complexity in the verification. “The problem was already challenging enough,” observed Mark Baker, director of product marketing at Atrenta. “Just looking at where SoC design was going was a collection of various IPs, the different communication protocols, the bus ... » read more

UPF-Friendly RTL
By Bernard Murphy - 13 Mar, 2014 - Comments: 0

On a recent customer visit, we were introduced to a new term – new to us at least – “UPF-friendly RTL”. While I hadn’t heard the term, I have been going on about the concept for some time – to the point, no doubt, of becoming terminally boring. We’ve had several customers quietly doing this for years, but now I’m starting to hear it from more customers, and from 1801 committee m... » read more

Power’s Impact On Hierarchy Modification
By Ann Mutschler - 16 Jan, 2014 - Comments: 2

RTL restructuring in which the logical hierarchy of a design is modified is usually done to manage complex designs. When power management is added to this task, new challenges crop up. Consider switchable power or voltage domains, which are a common way to manage power is to use switchable power or voltage domains. When implementing this technique, all the logic in such a domain must hang of... » read more

IEEE 1801 UPF Tutorial
By Various Writers - 22 Nov, 2013 - Comments: 0

This tutorial from DVCon 2013 covers the basics of Accellera UPF and then focuses on the features of IEEE 1801 that enable the description of more sophisticated power management systems. The tutorial also provides recommendations regarding migration from Accellera UPF to IEEE 1801 and the methodology changes that are required. And, it presents a UPF-based design flow highlighting the practical ... » read more

ARM Cortex-A53, UPF & FD-SOI
By Barry Pangrle - 07 Nov, 2013 - Comments: 0

The IEEE Standards Association Symposium on Electronic Design Automation (EDA) Interoperability was held on Oct. 24. I found the first session, Interoperability Challenges: Power Management in Silicon, with presentations by Erich Marschner of Mentor Graphics and Stuart Riches and Adnan Khan (both from ARM) to be particularly interesting. Earlier this year, the IEEE announced a new version of UP... » read more

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