Understanding UVM Coverage For RISC-V Processor Designs


Attempting to achieve complete RISC-V verification requires multiple methodologies employing a wide range of relevant tools, including: • Coverage driven simulation based on UVM constrained random methods and compliant with the Universal Verification Methodology (UVM) standard • Static and formal property verification • Equivalence checking • Emulation and FPGA based verific... » read more

Bugs That Kill


Are simulation-resistant superbugs stifling innovation? That is a question Craig Shirley, president and CEO of Oski Technology, asked a collection of semiconductor executives over dinner. Semiconductor Engineering was invited to hear that discussion and to present the key points of the discussion. To promote free conversation, the participants, who are listed below, asked not to be quoted di... » read more