tag: UVM

Hybrid Verification: The Only Way Forward
By Brian Bailey - 01 Dec, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

Blog Review: June 18
By Ed Sperling - 18 Jun, 2014 - Comments: 1

Mentor’s Vern Wnek recalls “a living hell” of being trapped in a small office for three weeks with a PCB designer who ate too much garlic and sweated profusely. This could be a reality TV series. What do engineers really think about UVM? Cadence's Richard Goering braved a 7 a.m. breakfast at DAC to hear a panel of experts, including reps from Intel, Ericsson, Imagination and Freescale,... » read more

Is Formal Ready To Displace Simulation?
By Brian Bailey - 21 May, 2014 - Comments: 2

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In part two, the panel focused on the subject of coverage and the ways in which formal coverage can be combined with simulation. In this segment we start exploring the impact that sequential equi... » read more

How To Improve Debug Productivity
By Ann Mutschler - 24 Apr, 2014 - Comments: 0

In the realm of SoC verification world, it often takes a very short amount of time to write the testbench and the code, and the rest of the time — up to 90% — is spent debugging. After all, verification is essentially finding the bugs in a design. Debugging essentially has evolved over the years on the same path and complexity curve as design. Now debugging needs to evolve to keep pace, ... » read more

Extending UVM To Analog
By Ann Mutschler - 24 Apr, 2014 - Comments: 2

As SoC complexity has grown, so too has the need to model the analog/mixed-signal content in a similar way as the digital content to make simulation easier. One way to do this is within the context of the Universal Verification Methodology (UVM). In fact, this can and is being done today with UVM as it stands, according to a number of industry sources. However, there is also growing interest... » read more

Does Formal Have You Covered?
By Brian Bailey - 24 Apr, 2014 - Comments: 1

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In this segment we start exploring those difficulties in more detail and the progress made with integrated coverage. Participating in the panel were Pete Hardee, director of product management fo... » read more

Blog Review: April 23
By Ed Sperling - 23 Apr, 2014 - Comments: 0

Mentor’s John Day looks backward through a smart rearview mirror from Nissan. No glare, even at night or at sunset, and a wider field of vision. You have to wonder why this technology took so long. Synopsys’ Karen Bartleson wonders when the IoT will actually arrive, given the delay in durable goods, a concern over security and the effects of government regulation. Answer: When we stop ta... » read more

Blog Review: April 16
By Ed Sperling - 16 Apr, 2014 - Comments: 0

Cadence’s Richard Goering attended a workshop on “extreme” scale design automation, which looked at where else EDA tools can be used—such as intelligent traffic lights. At least there are well-defined use cases. Mentor’s Nazita Saye has compiled five predictions from the 1964 New York World’s Fair that are worth revisiting. Three of them came true. Check out the ones that didn’... » read more

Biggest Verification Mistakes
By Ann Mutschler - 27 Mar, 2014 - Comments: 0

[getkc id="81" kc_name="SoC"]s today have more processors and more embedded software than ever, including drivers and middleware just to get the hardware working. This, in turn, requires more and better [getkc id="10" kc_name="verification"]. Add to the challenge the fact that there is no one way to do verification and it is easy to comprehend how critical it is to for hardware and software tea... » read more

Formal Is Set To Overtake Simulation
By Brian Bailey - 27 Mar, 2014 - Comments: 4

There has been a significant psychology change in the area of formal verification over the past couple of years. It’s no longer considered a fringe technology, and it’s no longer considered difficult to use. In fact, it has become a necessary part of the verification process. Semiconductor Engineering sat down with a panel of experts to find out what caused this change and what more we c... » read more

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