Extending UVM To Analog

By Ann Mutschler - 24 Apr, 2014 - Comments: 2

As SoC complexity has grown, so too has the need to model the analog/mixed-signal content in a similar way as the digital content to make simulation easier. One way to do this is within the context of the Universal Verification Methodology (UVM). In fact, this can and is being done today with UVM as it stands, according to a number of industry sources. However, there is also growing interest... » read more

Does Formal Have You Covered?

By Brian Bailey - 24 Apr, 2014 - Comments: 1

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In this segment we start exploring those difficulties in more detail and the progress made with integrated coverage. Participating in the panel were Pete Hardee, director of product management fo... » read more

Blog Review: April 23

By Ed Sperling - 23 Apr, 2014 - Comments: 0

Mentor’s John Day looks backward through a smart rearview mirror from Nissan. No glare, even at night or at sunset, and a wider field of vision. You have to wonder why this technology took so long. Synopsys’ Karen Bartleson wonders when the IoT will actually arrive, given the delay in durable goods, a concern over security and the effects of government regulation. Answer: When we stop ta... » read more

Blog Review: April 16

By Ed Sperling - 16 Apr, 2014 - Comments: 0

Cadence’s Richard Goering attended a workshop on “extreme” scale design automation, which looked at where else EDA tools can be used—such as intelligent traffic lights. At least there are well-defined use cases. Mentor’s Nazita Saye has compiled five predictions from the 1964 New York World’s Fair that are worth revisiting. Three of them came true. Check out the ones that didn’... » read more

Biggest Verification Mistakes

By Ann Mutschler - 27 Mar, 2014 - Comments: 0

[getkc id="81" kc_name="SoC"]s today have more processors and more embedded software than ever, including drivers and middleware just to get the hardware working. This, in turn, requires more and better [getkc id="10" kc_name="verification"]. Add to the challenge the fact that there is no one way to do verification and it is easy to comprehend how critical it is to for hardware and software tea... » read more

Formal Is Set To Overtake Simulation

By Brian Bailey - 27 Mar, 2014 - Comments: 4

There has been a significant psychology change in the area of formal verification over the past couple of years. It’s no longer considered a fringe technology, and it’s no longer considered difficult to use. In fact, it has become a necessary part of the verification process. Semiconductor Engineering sat down with a panel of experts to find out what caused this change and what more we c... » read more

Blog Review: March 12

By Ed Sperling - 12 Mar, 2014 - Comments: 0

Arteris’ Kurt Shuler is sounding the alarm bell for the semiconductor industry. He observes that system OEMs are hiring their own chip engineers. Well, that should wake up someone. Danger Will Robinson. Mentor’s Colin Walls points to a festering debate in the embedded software world about priorities and openness to learning new tools and approaches. Embedded software developers are a rat... » read more

Does It Take A Catastrophe?

By Linda Prowse Fosler - 20 Feb, 2014 - Comments: 0

What makes a company search for new verification methods and tools? Sometimes organizations change, proactively, because they are wise and want to avoid problems; but sadly, more often it is a catastrophe that forces change. This was the case with a large U.S. supplier of safety-critical and high-reliability ICs. After a failed chip, it finally moved from simply verifying the analog and digi... » read more

2014 Accellera Standards Are Built on Powerful Shoulders

By Accellera - 27 Jan, 2014 - Comments: 0

By Adam Sherer Looking out at the fresh snow coating the landscape here in Buffalo, it’s tempting to look toward 2014 and focus only on the fresh and new. However, if I’ve learned anything about this city from the day I arrived here as a freshman EE in 1984, it’s that you don’t bury your foundation. Instead, you recognize it as your greatest strength, the powerful shoulders upon whic... » read more

The Problem With EDA Standards

By Brian Bailey - 07 Nov, 2013 - Comments: 0

In the EDA industry, does standard mean the same as it does in most industries? The Free Dictionary defines it as: Something, such as a practice or a product, that is widely recognized or employed, especially because of its excellence. In the EDA industry, a standards body is the place where EDA companies and customers come together to try and bring about convergence, often in a new or emerging... » read more

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Knowledge Centers
Entities, people and technologies explored

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eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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tag: UVM