Blog Review: June 18

A living hell; UVM; tomato cars; shots fired; car-to-X communication; code mangling; Intel’s inroads; security; wearables; power analysis.

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Mentor’s Vern Wnek recalls “a living hell” of being trapped in a small office for three weeks with a PCB designer who ate too much garlic and sweated profusely. This could be a reality TV series.

What do engineers really think about UVM? Cadence’s Richard Goering braved a 7 a.m. breakfast at DAC to hear a panel of experts, including reps from Intel, Ericsson, Imagination and Freescale, discuss the biggest problems: complexity and register modeling.

Ansys’ Justin Nescott has identified five new engineering articles of note. Check out the research by Ford and Heinz to use tomato skins in car parts. There’s only one problem with that image: Heinz used to market itself as the slowest ketchup in the West, East, North And South.

Synopsys’ Mick Posner has a video about his antilag turbo system on his car. Interesting concept, but it sounds like a shooting gallery.

ARM’s Brad Nemire profiles the co-founder of Taipei Hackerspace, Gergely Imreh. Of particular note are his tip to a beginner developer and the future of expertise.

NXP’s Stefanie Linke looks into progress being made in Car-to-X communication, which will be one of the key technologies in driverless cars. Things are about to get very interesting on the highway.

Mentor’s Colin Walls examines a rather odd phenomenon during C++ compilation called mangling, which as you might expect is not a good thing.

Cadence’s Brian Fuller reports back on the DAC keynote by Intel chief security architect Ernie Brickell, who said hardware and software need to be designed in sync to plug security holes. Now if only the hardware and software engineers would talk to each other.

Mentor’s John Day looks at the new Intel In-Vehicle Solutions. As he notes, Intel’s IoT group reported $482 million in revenue in Q1. It looks as if Intel is making…well…inroads.

Cadence’s Richard Goering offers some insights into why Cadence bought Jasper—a deal that closed on Monday. Formal definitely and equivalency checking definitely are going mainstream, and now Cadence has a solid position in that market.

DAC chair Anne Cirkel reveals why she reviewed the permission levels for all of her iPhone apps.

And in case you missed last week’s Low Power-High Performance newsletter, here are some noteworthy blogs:

Executive Editor Ann Steffora Mutschler observes that the question of whether power really takes top priority boils down to definitions.

Cadence’s Brian Fuller says that until new standards, platforms and approaches are in place, expect some turbulence in the computer vision arena.

Mentor Graphics’ Chetandeep Singh and Ravi Tangirala team up to explain why early and accurate power analysis is critical.

Synopsys’ Namit Gupta contends the only way low-power CDC paths can be checked at RTL is if the CDC tool can infer the power network from the UPF description.

Ansys-Apache’s Aveek Sarkar says finFETs improve performance and reduce energy consumption, but they also add new design challenges.

ARM’s Ellie Stone predicts that wearable technology could become as large over the next decade as the mobile market is today.

Nvidia’s Barry Pangrle says it’s not just the clock speed that increases performance of a processor. Memories play a big role.

Atrenta’s Mark Baker notes that While EDA shifts its primary focus onto System Level Power Optimization, RTL power optimization is just hitting mainstream deployment.



  • Cheers for the mention, and picking up on the message to beginners and experts. 🙂 I see so much potential, and have to start doing things better. If you are ever in Taiwan, come visit the Hackerspace!