Four Requirements To Improve Chip Design Debug

By Taruna Reddy - 26 Aug, 2021 - Comments: 0

Debug has always been a painful and unavoidable part of semiconductor design and, despite many technological advances, it remains one of the dominant tasks in chip development. At one time, most bugs were detected and diagnosed on actual devices in the bring-up lab, where both visibility and controllability are severely limited. It is certainly true that debugging the results from pre-silicon t... » read more

Continuing Challenges For Open-Source Verification

By Brian Bailey - 01 Jun, 2021 - Comments: 1

Experts at the Table: This is the last part of the series of articles derived from the DVCon panel that discussed Verification in the Era of Open Source. It takes the discussion beyond what happened in the panel and utilizes some of the questions that were posed, but never presented to the panelists due to lack of time. Contributing to the discussion are Ashish Darbari, CEO of Axiomise; Serge L... » read more

Scaling Simulation

By Brian Bailey - 27 May, 2021 - Comments: 1

Without functional simulation the semiconductor industry would not be where it is today, but some people in the industry contend it hasn't received the attention and research it deserves, causing a stagnation in performance. Others disagree, noting that design sizes have increased by orders of magnitude while design times have shrunk, pointing to simulation remaining a suitable tool for the job... » read more

New Methodologies Create New Opportunities

By Brian Bailey - 27 Apr, 2021 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss what open source verification means today and what it should evolve into, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Ashish Darbari, CEO of Axiomise; Simon Davidmann, CEO of Imperas Software; Serge Leef, program manager in the Microsystems Technology Office at DARPA; Tao Liu, staff hardwa... » read more

Verification’s Inflection Point

By Brian Bailey - 14 Jan, 2021 - Comments: 0

Functional verification is nearing an inflection point, brought on by rising complexity and the many tentacles that are intermixing it with other disciplines. New abstractions or different ways to approach the problems are needed. Being a verification engineer is no longer enough, except for those whose concerns is block-level verification. Most of the time and effort spent in verification i... » read more

Week In Review: Design, Low Power

By Jesse Allen - 18 Dec, 2020 - Comments: 0

Tools, Cloud, IP Valtrix Systems updated its STING design verification tool for RISC-V based CPU and SoC implementations. Version 1.9.0 adds support to verify recent changes to the RISC-V user and privilege specifications, including draft versions of the vector and bit manipulation standard extensions. Preliminary support for the draft version of the RISC-V hypervisor extension has also been a... » read more

Verification Convergence: Problem Definition

By Hagai Arbel - 30 Nov, 2020 - Comments: 0

A while ago, I had to go to the ER with my friend who suddenly had a numb feeling in his face. He felt okay (and everything else is okay with him), but better be safe than sorry. While the doctor examined him I noticed that before tracing the problem itself, she asked some questions to rule-out a problem she was already familiar with and that can manifest itself in similar ways. Only then, a... » read more

Blog Review: Oct. 7

By Jesse Allen - 07 Oct, 2020 - Comments: 0

In a blog for Arm, University of Southampton PhD student Sivert Sliper looks at how energy-driven and intermittent computing could be used to power trillions of IoT devices and introduces a SystemC-based simulator for such systems. Mentor's Chris Spear explains why transaction classes should extend from uvm_sequence_item rather than uvm_transaction when designing UVM testbenches. Cadence'... » read more

New Uses For Assertions

By Ann Mutschler - 24 Sep, 2020 - Comments: 0

Assertions have been a staple in formal verification for years. Now they are being examined to see what else they can be used for, and the list is growing. Traditionally, design and verification engineers have used assertions in specific ways. First, there are assertions for formal verification, which are used by designers to show when something is wrong. Those assertions help to pinpoint wh... » read more

How UVM Callbacks Simplify Assertion Validation

By Akshay Sarup - 13 Aug, 2020 - Comments: 0

By Akshay Sarup and Mark Olen Assertions bring immediate benefits to the whole design and verification cycle; thus any challenges engineers face in coding and testing them are worth resolving. When a large number of assertions are to be validated, callbacks save time by eliminating the need to code a new sequence for each scenario. Callbacks also provide more dynamic and fine-grained cont... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?