Week In Review: Design, Low Power

By Jesse Allen - 17 Jan, 2020 - Comments: 0

Inphi Corporation and Synopsys finalized the acquisition of eSilicon. Synopsys acquired certain IP assets from eSilicon, including TCAMs and multi-port memory compilers, as well as its Interface IP portfolio with High-Bandwidth Interface (HBI) IP and a team of R&D engineers; it did not disclose terms of the deal. Inphi Corporation bought the rest of the company for approximately $216 millio... » read more

Portable Stimulus And Digital Twins

By Brian Bailey - 25 Nov, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemens Business; Tom Anderson, technical marketing consultant for OneSp... » read more

Week In Review: Design, Low Power

By Jesse Allen - 22 Nov, 2019 - Comments: 1

Accellera formed the Universal Verification Methodology Analog/Mixed-Signal Working Group (UVM-AMS WG), which will work to develop a standard that will provide a unified analog/mixed-signal verification methodology based on UVM to improve the verification of AMS integrated circuits and systems. “Our objective is to standardize a method to drive and monitor analog/mixed-signal nets within UVM,... » read more

Extending Portable Stimulus

By Brian Bailey - 16 Oct, 2019 - Comments: 0

The Growing Impact Of Portable Stimulus

By Brian Bailey - 26 Sep, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Dave Kelf, chief marketing officer for Breker Verification Systems; Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemen... » read more

Evolution Of Verification Engineers

By Brian Bailey - 22 May, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions archit... » read more

Week In Review: Design, Low Power

By Jesse Allen - 26 Apr, 2019 - Comments: 0

A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

Data-Driven Verification Begins

By Ed Sperling - 27 Mar, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss data-driven verification with Yoshi Watanabe, senior software architect at Cadence; Hanan Moller, systems architect at UltraSoC; Mark Conklin, principal verification engineer at Arm; and Hao Chen, senior design engineer at Intel. What follows are excerpts of that conversation, which was conducted in front of a live audience at DVCon. (L-R) Yosh... » read more

Closing Functional And Structural Coverage On RTL Generated By High-Level Synthesis

By Mentor, a Siemens Business - 14 Mar, 2019 - Comments: 0

Most hardware design teams have a verification methodology that requires a deep understanding of the RTL to reach their verification goals, but this type of methodology is difficult to apply to the machine generated RTL from High-level Synthesis (HLS). This paper describes innovative techniques to use with existing methodologies, for example the Universal Verification Methodology (UVM), to clos... » read more

Can Debug Be Tamed?

By Brian Bailey - 28 Feb, 2019 - Comments: 0

Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

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tag: UVM

Week In Review: Design, Low Power

Portable Stimulus And Digital Twins

Week In Review: Design, Low Power

Extending Portable Stimulus

The Growing Impact Of Portable Stimulus

Evolution Of Verification Engineers

Week In Review: Design, Low Power

Data-Driven Verification Begins

Closing Functional And Structural Coverage On RTL Generated By High-Level Synthesis

Can Debug Be Tamed?