Week In Review: Design, Low Power

Analog/mixed-signal verification standard in the works; FPGA prototyping; connectivity analytics.


Accellera formed the Universal Verification Methodology Analog/Mixed-Signal Working Group (UVM-AMS WG), which will work to develop a standard that will provide a unified analog/mixed-signal verification methodology based on UVM to improve the verification of AMS integrated circuits and systems. “Our objective is to standardize a method to drive and monitor analog/mixed-signal nets within UVM, including stimulus, scoreboarding, and analysis,” stated Patrick Lynch, UVM-AMS WG Chair. “We will also work to define a framework for the creation of analog/mixed-signal verification components by introducing extensions to digital-centric verification IP.” The WG will initially focus its efforts to consolidate industry requirements of UVM-AMS and produce a whitepaper that will help define the scope of the standardization effort. The language reference manual, which defines the UVM-AMS standard, and a supporting reference implementation will follow.

Pro Design launched a new FPGA prototyping solution containing 4 pluggable Stratix 10 GX 10M FPGA modules. The quad system offers a capacity of up to 240 million ASIC gates, and up to nine proFPGA quad systems with 36 FPGA modules overall can be connected together to increase the capacity up to 2 billion ASIC gates. It also offers 64 extension sites, with a total of 8304 I/Os, 192 high-speed serial transceivers, and is fully compatible with previous proFPGA generations.

UltraSoC added PCIe and gigabit Ethernet connectivity to its embedded analytics architecture, supporting debug and performance optimization through IP modules and reference software in datacenters, high-performance computing, AI and storage applications.

Faraday Technology’s fundamental IP, including multi-Vt standard cell libraries, ECO libraries, IO libraries, PowerSlash kit, and memory compilers, is now available on UMC’s 22nm ultra-low-power (ULP) and ultra-low-leakage (ULL) processes.

Samsung Foundry adopted Synopsys’ Custom Design Platform, based on the Custom Compiler design environment, to design IP for its 5nm Low-Power Early (LPE) process with EUV lithography. To support deployment, an analog/mixed-signal reference flow for the platform and a 5LPE interoperable process design kit (iPDK) have been developed and are available now for Samsung Foundry customers.

Graphcore selected Mentor’s Questa software for simulation and verification of its Colossus GC2 Intelligence Processing Unit (IPU), which consists of 23.6 billion transistors and more than 1,000 IPU-Cores. Graphcore also used Mentor’s Tessent DFT and silicon bring-up tools.

ANSYS and Autodesk teamed up to integrate Autodesk’s Fusion 360 integrated design and manufacturing software with ANSYS Mechanical simulation solutions, making Fusion 360 results automatically available in ANSYS Mechanical for further refinement and validation. ANSYS will also work with Rockwell Automation on tools for creating digital twins and managing digital threads. Additionally, Porsche Motorsport is using ANSYS simulation tools to create an advanced electric powertrain that will increase energy efficiency for the Porsche 99X Electric, the company’s first fully electric race car.

Check out upcoming industry events and conferences: Accellera will hold a Proposed Working Group meeting on a potential standard for FMEDA tool interoperability on Dec. 6 at NXP in Munich, Germany. The RISC-V Summit will include talks, an expo, and tutorials on the open ISA Dec. 10-12 in San Jose, CA. Next year, DesignCon will take place January 28-30 in Santa Clara, CA, with a focus on board and high-speed communications design.


Kevin Cameron says:

There’s little point in an Accellera UVM-AMS standard when SystemVerilog doesn’t actually support AMS. The only AMS standard is Verilog-AMS, and it doesn’t support UVM.

The SV-DC committee which is supposed to address this has failed to solve any of the issues so far. It is all fixable, but nobody seems to have the will to pay for it on the customer side, and EDA companies won’t budge.

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