Managing Complexity And A Left Shift: Reconfigurable Mixed-Signal Circuits For Complex Integrated Systems


By Björn Zeugmann and Benjamin Prautsch The chip market is growing worldwide; it’s projected to nearly double by 2030 to over one trillion dollars. Most of this market is made up of digital functions in the form of logic, microprocessors, and memory. Although analog ICs account for only around 15% of the total, they are key components for overall systems and are therefore almost always pr... » read more

Formal Verification of Security Properties On RTL Designs


A technical paper titled “RTL Verification for Secure Speculation Using Contract Shadow Logic” was published by researchers at Princeton University, MIT CSAIL, and EPFL. Abstract: "Modern out-of-order processors face speculative execution attacks. Despite various proposed software and hardware mitigations to prevent such attacks, new attacks keep arising from unknown vulnerabilities. Thus... » read more

Here At Last! Automated Verification Of Heterogeneous 2D/3D Package Connectivity


By Michael Walsh and Jin Hou with Todd Burkholder The heterogeneous integration of multiple ICs in a single package along with high-performance, high-bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making i... » read more

PCIe 6.0 Address Translation Services: Verification Challenges And Strategies


Address Translation Services (ATS) is a mechanism in PCIe that allows devices to request address translations from the Input/Output Memory Management Unit (IOMMU). This is particularly important where devices need to access virtual memory. ATS enhances performance by enabling devices to cache translations, reducing the latency associated with memory access. This blog delves into the semantics ... » read more

NVMs: In-Memory Fine-Grained Integrity Verification Technique (Intel Labs, IISc)


A new technical paper titled "iMIV: in-Memory Integrity Verification for NVM" was published by researchers at Intel Labs and Indian Institute of Science (IISc), Bengaluru. Abstract "Non-volatile Memory (NVM) could bridge the gap between memory and storage. However, NVMs are susceptible to data remanence attacks. Thus, multiple security metadata must persist along with the data to protect th... » read more

Holistic Verification and Validation of Automotive IP for Functional Safety SoCs


Automotive functional safety systems have strict requirements to help avoid damages to life and property in case of a failure. As technology becomes more complex, there are increasing safety-related risks from systematic failures and random hardware failures that must be considered during product development. Standards like ISO 26262 provide guidance to mitigate such safety-related risks, by de... » read more

Verification Tools Straining To Keep Up


Verification engineers are the unsung heroes of the semiconductor industry, but they are at a breaking point and desperately in need of modern tools and flows to deal with the rapidly increasing pressures. Verification is no longer just about ensuring that functionality is faithfully represented in an implementation. That alone is an insolvable task, but verification has taken on many new re... » read more

Data Coherence Across Silos And Hierarchy


Shift left has become a rallying cry for the chip design industry, but unless coherent data can flow between the groups being impacted, the value may not be as great as expected. Shift left is a term that encompasses attempts to bring analysis and decision-making forward in the development process. The earlier an issue can be found, the less of a problem it ultimately becomes. But in many ca... » read more

An LLM Approach For Large-Scale SoC Security Verification And Policy Generation (U. of Florida)


A technical paper titled “SoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation” was published by researchers at the University of Florida. Abstract: "Contemporary methods for hardware security verification struggle with adaptability, scalability, and availability due to the increasing complexity of the modern system-on-chips (SoCs). ... » read more

Toward A Software-Defined Hardware World


Software-defined hardware may be the ultimate Shift Left approach as chip design grows closer to true co-design than ever with potential capacity baked into the hardware, and greater functionality delivered over the air or via a software update. This marks another advance in the quest for lower power, one that’s so revolutionary that it’s upending traditional ideas about model-based systems... » read more

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