Does Hardware/Software Verification Have To Be Broad And Deep? Check Out DVCon 2017


DVCon 2017 is upon us next week and even though it is called the “Design and Verification” conference, it is rising more and more to the system level. One of the aspects of interest is how verification seems to simultaneously become broader—covering more aspects to verify like software, power and performance—while also becoming more deep when it comes to application domains and their sp... » read more

Find Your Way To San Jose Next Week… For DVCon, Of Course!


If you’re asked “Do you know the way to San Jose?” in the next few days, chances are it’s a newbie to DVCon. Everyone else in chip design verification knows the way to the annual Design and Verification Conference and Exhibition about to convene at the San Jose DoubleTree Hotel. This year’s program is stacking up to be an insightful and educational four days of tutorials, paper ses... » read more

Massive SoC Designs Open Doors To New Era In Simulation


As system-on-chip (SoC) designs have grown in size, simulation technologies have had to evolve dramatically to keep pace. We’re now at an inflection point where both speed and capacity are essential and new simulation technologies are needed to meet the demands. In this paper, we’ll discuss how simulation has evolved and examine how new technologies such as the Cadence RocketSimTM Parallel ... » read more

Implementing Fan-Out Wafer-Level Packaging with Mentor Graphics


Fan-out wafer-level packaging (FOWLP) is a new high-density packaging technology that is rapidly gaining popularity. What is it? Who needs it? How do you take advantage of it? What limitations does it have? Learn all about FOWLP and our comprehensive tool integration and support for the design and verification of FOWLP products. To read more, click here. » read more

Formal Verification Takes Safety-Critical Applications For A Drive


The high reliability of safety-critical chips for automotive applications is a well-known imperative for today’s higher-end cars and as driverless cars move closer to reality. Uber, in fact, is testing autonomous cars in Boston of all places, where aggressive driving reigns supreme and honking the horn is considered an art form. As automotive manufacturers realize that their differentiatio... » read more

Hybrid Simulation Picks Up Steam


As electronic products shift from hardware-centric to software-directed, design teams are relying increasingly on a simulation approach that includes multiple engines—and different ways to use those engines—to encompass as much of the system as possible. How engineers go about using these approaches, and even how they define them, varies greatly from one company to the next. Sometimes it... » read more

What Can Go Wrong In Automotive


Semiconductor Engineering sat down to discuss automotive engineering with Jinesh Jain, supervisor for advanced architectures in Ford’s Research and Innovation Center in Palo Alto; Raed Shatara, market development for automotive infotainment at [getentity id="22331" comment="STMicroelectronics"]; Joe Hupcey, verification product technologist at [getentity id="22017" e_name="Mentor Graphics"]; ... » read more

Multiple Dimensions Of Low-Power Verification With Portable Stimulus


There is little doubt that designing for low power is one of the biggest challenges for today’s system-on-chip (SoC) devices. The need to minimize power consumption is clear for the vast array of portable electronic devices that we use every day. Consumers expect most of their gadgets to last multiple days before they require recharging, and low-power design is the key to extending battery li... » read more

2017: Manufacturing And Markets


While the industry is busy chatting about the end of Moore's Law and a maturing of the semiconductor industry, the top minds of many companies are having none of it. A slowdown in one area is just an opportunity, in another and that is reflected in the predictions for this year. As in previous years, Semiconductor Engineering will look back on these predictions at the end of the year to see ... » read more

The Fundamental Power States For UPF Modeling And Power Aware Verification


The IEEE 1801-2015 specifies the new semantics of power states through the ‘add_power_state’ UPF command. This new construct primarily allows incremental refinement of power states for power domains and its associated supply sets. The refinement concepts are actually originated from the fundamental conceptual set of power states termed as indefinite, definite, and deferred power states. In ... » read more

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