New Techniques To Analyze And Reduce Etch Variation

By Coventor - 25 Jan, 2017 - Comments: 1

Time division multiplex (TDM) plasma etch processes (commonly referred to as Deep Reactive ION Etching [“DRIE”]) use alternating deposition and etch steps cyclically to produce high aspect ratio structures on a silicon substrate. These etch processes have been widely applied in the manufacturing of silicon MEMS devices, and more recently in creating through silicon vias in 3D silicon struct... » read more

Defect Evolution In Next-Generation Extreme Ultraviolet Lithography

By Coventor - 21 Sep, 2016 - Comments: 0

Extreme ultraviolet (EUV) lithography is a promising next generation lithography technology that may succeed optical lithography at future technology nodes. EUV mask infrastructure and manufacturing of defect-free EUV mask blanks is a key near term challenge in the use of EUV lithography. Virtual fabrication is a computerized technique to perform predictive, three dimensional modeling of sem... » read more

Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

by Brian Bailey

tag: virtual fabrication

New Techniques To Analyze And Reduce Etch Variation

Defect Evolution In Next-Generation Extreme Ultraviolet Lithography

Trending Articles

NAND Flash Targets 1,000 Layers

Testing For Thermal Issues Becomes More Difficult

Auto Chip Aging Accelerates In Hot Climates

Is In-Memory Compute Still Alive?

Top-Down Vs. Bottom-Up Chiplet Design

Knowledge Centers
Entities, people and technologies explored

Related Articles

Shift Left Is The Tip Of The Iceberg

Partitioning In The Chiplet Era

NAND Flash Targets 1,000 Layers

AI’s Role In Chip Design Widens, Drawing In New Startups

What Comes After HBM For Chiplets

Memory Fundamentals For Engineers

New AI Processors Architectures Balance Speed With Efficiency

Defining The Chiplet Socket

Sponsors

Recent Comments

About

Navigation

Connect With Us

tag: virtual fabrication

New Techniques To Analyze And Reduce Etch Variation

Defect Evolution In Next-Generation Extreme Ultraviolet Lithography

Trending Articles

NAND Flash Targets 1,000 Layers

Testing For Thermal Issues Becomes More Difficult

Auto Chip Aging Accelerates In Hot Climates

Is In-Memory Compute Still Alive?

Top-Down Vs. Bottom-Up Chiplet Design

Knowledge Centers Entities, people and technologies explored

Related Articles

Shift Left Is The Tip Of The Iceberg

Partitioning In The Chiplet Era

NAND Flash Targets 1,000 Layers

AI’s Role In Chip Design Widens, Drawing In New Startups

What Comes After HBM For Chiplets

Memory Fundamentals For Engineers

New AI Processors Architectures Balance Speed With Efficiency

Defining The Chiplet Socket

Sponsors

Newsletter Signup

Popular Tags

Recent Comments

About

Navigation

Connect With Us

Knowledge Centers
Entities, people and technologies explored