tag: VMM

In-Memory Computing: Assessing Multilevel RRAM-Based VMM Operations
By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A new technical paper titled "Experimental Assessment of Multilevel RRAM-Based Vector-Matrix Multiplication Operations for In-Memory Computing" was published by researchers at IHP (the Leibniz Institute for High Performance Microelectronics). Abstract: "Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computin... » read more

Crisis In Data
By Ed Sperling - 28 Feb, 2019 - Comments: 0

The push toward data-driven design, debug, manufacturing and reliability holds huge promise, but the big risk is none of this will happen in an organized fashion and everyone will be frustrated. One of the clear messages coming out of DVCon this week is that standards need to be established for data. Even within large chipmakers and systems companies, the data they extract from tools is not ... » read more

Mentor, Cadence Join Forces
By Ed Sperling - 15 Jun, 2015 - Comments: 0

Mentor Graphics and Cadence have agreed to create a single binary interface for their respective simulation and emulation platforms, allowing debug tools from one vendor to run on the other's platforms. The two have invited [getentity id="22035" e_name="Synopsys"] to join their initiative, as well. So far, there is no decision. The move proposes a single API for both [getentity id="22032"... » read more

The Problem With EDA Standards
By Brian Bailey - 07 Nov, 2013 - Comments: 0

In the EDA industry, does standard mean the same as it does in most industries? The Free Dictionary defines it as: Something, such as a practice or a product, that is widely recognized or employed, especially because of its excellence. In the EDA industry, a standards body is the place where EDA companies and customers come together to try and bring about convergence, often in a new or emerging... » read more

Best Practices In Verification
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler The advent of advanced verification methodologies such as the UVM and its predecessors VMM and OVM has changed the verification landscape in many ways. Design and verification teams used to worry about simulator performance (i.e., how fast the simulator runs a particular test case), but the introduction of constrained-random stimulus and functional coverage and associ... » read more

Verifying Low-Power Designs
By Ed Sperling - 14 Jan, 2010 - Comments: 0

By Ed Sperling Power islands and multiple voltages used to be reserved for cell phone and process companies, but as more companies move to 65nm and 45nm process nodes these approaches to saving power—particularly in chips with multiple cores—are becoming mainstream. The problem isn’t in the architecture of the chips, although that certainly brings its own set of challenges. More and m... » read more

Experts At The Table: Rising Complexity Meets Verification
By Ed Sperling - 18 Dec, 2009 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss rising complexity and its effects on verification with Barry Pangrle, solutions architect for low power design and verification at Mentor Graphics; Tom Borgstrom, director of solutions marketing at Synopsys; Lauro Rizzatti, vice president of worldwide marketing at EVE, and Prakash Narain, president and CEO Real Intent. What follows are... » read more

Boost For Verification Methodologies
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Synopsys introduced enhancements to its Verification Methodology Manual and Cadence began detailing new enhancements in its Open Verification Methodology. Both programs are in beta, yet they offer steps forward toward easing one of the biggest problem areas in chip development. With verification still consuming 70% or more of the non-recurring engineering costs of semicondu... » read more

The Next Problem In Verification
By Ed Sperling - 14 May, 2009 - Comments: 0

Last week’s blog on OVM vs. VMM was like a match on dry timber, which is probably a bad analogy to make in California these days. Weeding through the comments—both on the record and off, and there was plenty more off the record—it appears there’s plenty of work under way to bridge the two worlds, but there’s an inverse amount of information available to the people who use one or the... » read more

VMM vs. OVM Becomes More Important
By Ed Sperling - 07 May, 2009 - Comments: 0

For all the talk about VMM vs. OVM and how it doesn’t matter…well, apparently it does.   It’s not that one verification environment is so much better than the other. That’s like saying one religion is better than another. People kill each other over those kinds of statements. And the truth is, there are plenty of people who will argue for and against each side.   Strangely, when... » read more

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