tag: von Neumann bottleneck

SRAM-Based IMC For Cryogenic CMOS Using Commercial 5 nm FinFETs
By Technical Paper Link - 27 Sep, 2023 - Comments: 0

A technical paper titled “Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs” was published by researchers at University of Stuttgart, Indian Institute of Technology Kanpur, University of California Berkeley, and Technical University of Munich. Abstract: "Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the co... » read more

Applying a Floating Gate Field Effect Transistor To A Logic-in-Memory Application Circuit Design
By Technical Paper Link - 19 Sep, 2023 - Comments: 0

A technical paper titled “Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)” was published by researchers at Konkuk University, Korea National University of Transportation, Samsung Electronics, and Sungkyunkwan University. Abstract: "The high data throughput and high energy efficiency required recently are increasingly difficult to implement... » read more

An Energy-Efficient 10T SRAM In-Memory Computing Macro Architecture For AI Edge Processor
By Technical Paper Link - 28 Aug, 2023 - Comments: 0

A technical paper titled “An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor” was published by researchers at Atal Bihari Vajpayee-Indian Institute of Information Technology and Management (ABV-IIITM). Abstract: "In-Memory Computing (IMC) is emerging as a new paradigm to address the von-Neumann bottleneck (VNB) in data-intensive applications.... » read more

A Step Towards Eliminating The Von-Neumann Bottleneck By Co-locating Photonic Computing Elements And Non-Volatile Memory 
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Non-volatile heterogeneous III-V/Si photonics via optical charge-trap memory” was published by researchers at Hewlett Packard Enterprise. "We demonstrate, for the first time, non-volatile charge-trap flash memory (CTM) co-located with heterogeneous III-V/Si photonics. The wafer-bonded III-V/Si CTM cell facilitates non-volatile optical functionality for a variety... » read more

Compute-In Memory Accelerators Up-End Network Design Tradeoffs
By Katherine Derbyshire - 21 May, 2020 - Comments: 0

An explosion in the amount of data, coupled with the negative impact on performance and power for moving that data, is rekindling interest around in-memory processing as an alternative to moving data back and forth between the memory and the processor. Compute-in-memory (CIM) arrays based on either conventional memory elements like DRAM and NAND flash, as well as emerging non-volatile memori... » read more

3D Neuromorphic Architectures
By Katherine Derbyshire - 11 Dec, 2017 - Comments: 1

Matrix multiplication is a critical operation in conventional neural networks. Each node of the network receives an input signal, multiplies it by some predetermined weight, and passes the result to the next layer of nodes. While the nature of the signal, the method used to determine the weights, and the desired result will all depend on the specific application, the computational task is simpl... » read more

Toward Neuromorphic Designs
By Katherine Derbyshire - 25 Oct, 2017 - Comments: 1

Part one of this series considered the mechanisms of learning and memory in biological brains. Each neuron has many fibers, which connect to adjacent neurons at synapses. The concentration of ions such as potassium and calcium inside the cell is different from the concentration outside. The cellular membrane thus serves as a capacitor. When a stimulus is received, the neuron releases neur... » read more

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