3D ICs: No Simple Answers

By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Pallab Chatterjee Just how ready is the semiconductor industry for stacked die? That was the subject of a recent panel discussion involving ARM, Atrenta, Xilinx, Samsung and Mentor Graphics. The reasoning behind 3D stacking is becoming clearer at each node. I/O count and delay times are forcing different configurations, but the time frames for these changes and the gating constraints are... » read more

Special Report: Using FPGAs For 3D Stacking

By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Xilinx is developing a 3D architecture for its FPGAs and Actel has been approached by SoC makers to use its flash-based FPGA as a layer in a 3D IC stack. Both approaches could radically alter the fundamental equation about the tradeoffs between FPGAs and ASICs—particularly the power and performance overhead normally associated with programmable logic. Xilinx declined to com... » read more

Where SoCs Don’t Go

By Ed Sperling - 22 Apr, 2010 - Comments: 0

By Pallab Chatterjee The National Association of Broadcaster show is the one place where you can be sure to find some of the most advanced technology on the planet—the kind of stuff used to broadcast, capture and edit 3D content. But while the market for this kind of technology is growing, the quantities of like products are still not high enough to warrant ASICs. It’s a world dominated... » read more

Integrated IP Goes Vertical

By Ed Sperling - 25 Mar, 2010 - Comments: 0

By Ed Sperling The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that are pre-tested for specific vertical markets, and new companies are sprouting up to make it easier to put even broader collections of IP together in meaningful ways. It’s difficult to te... » read more

Emulation 2010

By Ann Mutschler - 25 Mar, 2010 - Comments: 0

By Ann Steffora Mutschler In an industry that was once fraught with patent infringement lawsuits, hostile takeovers and other exciting corporate warfare, the hardware-assisted emulation market has quieted down considerably. That doesn’t mean it has lost its luster, though. It still plays an integral, if not ever-increasing and expanding, role in the verification efforts of most semiconductor... » read more

The FPGA Alternative

By Various Writers - 31 Oct, 2009 - Comments: 0

By Geoffrey James Until a few years ago, SoC designers focused almost exclusively on ASICs. While it was theoretically possible to create an SoC design for an FPGA, the programmable chips were too bulky and pricey to be useful for much more than prototyping. Today, however, designers are increasingly turning to FPGAs for their SOC targets for production systems. Why the sudden upsurge in So... » read more

Making Connections

By Ed Sperling - 28 Oct, 2009 - Comments: 0

By Ed Sperling The world is still full of engineers who can build fast interconnects to things like PCI Express or USB 2.0 who can create complex schematics for determining the connections between a processor core, memory, logic and various IP blocks on a piece of silicon. But over the next several years, many of those engineers will have to figure out new ways to make a living. The numbe... » read more

FPGA Vendors Throw Kitchen Sink at Power-Consumption Issues

By Brian Fuller - 10 Jun, 2009 - Comments: 0

By Brian Fuller In the storied history of semiconductors, each era finds vendors generally attaching their strategy to a trendy application segment to differentiate themselves. For years, IC vendors were “computer companies.” Then they were in the “communications” business and more recently they were all about “consumer.” But the evolution of technology has forced a re-assessm... » read more

Soft Errors Create Tough Problems

By Ed Sperling - 28 Apr, 2009 - Comments: 0

By Ed Sperling Single event upsets used to be as rare as some elements on the Periodic Table, with the damage they could cause relegated more to theory than reality. Not anymore. At 90nm, what was theory became reality. And at 45nm, the events are becoming far more common, often affecting multiple bits in increasingly dense arrays of memory and now, increasingly, in the logic. Known alter... » read more

Writing Application Software Directly To The Metal

By Ed Sperling - 13 Mar, 2009 - Comments: 0

By Ed Sperling How necessary is an operating system? That question would have been considered superfluous a decade ago, possibly even blasphemous and career-limiting. But it now is beginning to surface in low-power discussions, particularly in compute-intensive applications where performance and power are both critical. General-purpose operating systems constantly call on the processor fo... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?