Bespoke Silicon Rattles Chip Design Ecosystem

By Ann Mutschler - 19 Oct, 2022 - Comments: 0

Bespoke silicon developers are shaking up relationships, priorities, and methodologies across the semiconductor industry, creating demand for skills that cross traditional boundaries, and driving new business models that leverage these enormous investments. Bespoke silicon designers today are a rare breed, capable of understanding the unique requirements of a specific domain, as well as a gr... » read more

Week In Review: Design, Low Power

By Jesse Allen - 08 Jul, 2022 - Comments: 0

Tools, IP, design Infineon Technologies acquired NoBug, a provider of design verification services. The acquisition will help Infineon expand its IoT R&D business in eastern Europe. “This considerable increase in superior verification know-how lets Infineon offer its customers more of its leading products at a reduced time-to-market,” said Guenter Krasser, Vice President and Managing D... » read more

Week In Review: Design, Low Power

By Jesse Allen - 01 Jul, 2022 - Comments: 0

IP, design Arm unveiled a number of new CPUs and GPUs. Based on the Armv9 architecture, the Cortex-X3 aims to improve single-threaded performance and targets a range of benchmarks and applications. The Cortex-A715 focuses on efficient performance, delivering a 20% energy efficiency gain and 5% performance uplift compared to Cortex-A710. In addition, the Cortex-A510 and DSU-110 were updated to ... » read more

Week In Review: Design, Low Power

By Jesse Allen - 05 Nov, 2021 - Comments: 0

Business Synopsys acquired Concertio, a provider of AI-powered performance optimization software. The acquisition will bolster Synopsys' silicon lifecycle management platform SiliconMAX SLM with the addition of Concertio's autonomous software agent that, when installed on the target system, continuously monitors the interactions between operating applications and the underlying system enviro... » read more

Using Agile Methods For Hardware

By Ann Mutschler - 28 Jan, 2016 - Comments: 11

[getkc id="182" kc_name=agile development"] methodology for software is getting a much closer look by hardware teams these days, because what used to work in SoC design and verification isn't working nearly as well with rising complexity. Development processes need to be constantly evolved to determine how to be more productive, deliver higher quality, cut costs in development, and how to g... » read more

Blog Review: Dec. 30

By Jesse Allen - 30 Dec, 2015 - Comments: 0

It's been a quiet week on the blog front. If you're looking for a bit of downtime while you enjoy the New Year, we present thoughts on what's happened this year and what may be to come from last week's System-Level Design newsletter: Editor in Chief Ed Sperling finds acquisitions and the leading edge of design defined 2015, but other changes are ahead. Technology Editor Brian Bailey obser... » read more

HW Vs. SW: Who’s Leading Whom?

By Brian Bailey - 29 Oct, 2015 - Comments: 6

In the past, technologies were developed in the software world that have languished until they were taken up by the hardware community. Then they were refined and polished and became fully integrated into the hardware development and verification flow. Examples are lint and formal. That was followed by attempts to migrate methodologies, such as object-oriented programming, which is the basis fo... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: XtremeEDA

Bespoke Silicon Rattles Chip Design Ecosystem

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Using Agile Methods For Hardware

Blog Review: Dec. 30

HW Vs. SW: Who’s Leading Whom?