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Week In Review: Design, Low Power

Electromigration and IR drop tool; hardware security verification; RISC-V reference model; barn owl-inspired localization; integrated quantum processing units; Infineon buys NoBug.

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Tools, IP, design

Infineon Technologies acquired NoBug, a provider of design verification services. The acquisition will help Infineon expand its IoT R&D business in eastern Europe. “This considerable increase in superior verification know-how lets Infineon offer its customers more of its leading products at a reduced time-to-market,” said Guenter Krasser, Vice President and Managing Director of Infineon Romania. “The acquisition will also further bolster Infineon Romania as a growth location for R&D in Europe and opens up ample new development opportunities for our engineers.” Founded in 1998, NoBug is located in Romania and Serbia. Terms of the deal were not disclosed.

Cadence unveiled a custom electromigration and IR drop (EM-IR) solution. Voltus-XFi Custom Power Integrity Solution offers transistor-level EM-IR extraction, simulation, analysis, and debugging with foundry-supported SPICE-level accuracy for power integrity signoff. It allows customers to view violations, zoom into interesting areas and overlay results in the Virtuoso platform for identification and violation fixing. Samsung Electronics, The Six Semiconductor, and Elevate Semiconductor noted adopting the tool. “To address the industry’s most complex automatic test equipment challenges, a robust power network is critical for us as an integrated circuit provider,” said Simon Leigh, vice president of engineering at Elevate Semiconductor. “Cadence’s Voltus-XFi solution enables us to run EM-IR analysis at full chip, which we could not do with our existing solution. We are adopting the solution for full production use.”

Optima Design Automation announced a new hardware security verification solution. Optima-SEC enables the high-performance pre-silicon verification of fault injection attacks and certifies the counter-measures adopted against such attacks that target the extraction of secret information from semiconductors leveraging side-channel effects. “Optima-SEC provides a specialized layer on top of high-performance fault-simulation that allows the modeling of any type of security attacks. Built-in models for laser-attack and EM-attack are also provided for expedited testing,” said Jamil R. Mazzawi, President and CEO of Optima Design Automation.

Samsung adopted Ansys’ electromagnetic simulation portfolio for its advanced chip designs, including 5G/6G. Samsung cited the ability to reduce time to market by two to three weeks on smaller designs and up to two months for complex designs.

Delta Electronics used Infineon’s CoolSiC MOSFET technology in its latest 1.4 kW server power supply. It also used Infineon’s CoolGaN technology and EiceDRIVER gate driver ICs in its 1.6 kW Titanium gaming power platform.

Professional services firm Accenture closed its acquisition of XtremeEDA, a provider of silicon design and verification services. “By combining XtremeEDA’s strong and deep experience in advance silicon design with Accenture’s Cloud First capabilities, we are poised to deliver more value for clients in specialized hardware, distributed cloud, decentralized edge computing and complex security needs,” said Jeffrey Russell, president of Accenture in Canada. XtremeEDA was founded in 2002 and is based in Ottawa, Canada. Terms of the deal were not disclosed.

The Center for Security and Emerging Technology issued a report on the Chinese military’s acquisition of high-end AI chips. They found that the vast majority of chips bought by the Chinese People’s Liberation Army were designed in the U.S. and manufactured in Taiwan and South Korea, rather than domestic suppliers. The report lays out why current approaches to export controls may be counterproductive and suggests that the United States expand its collection of open-source intelligence and adopt new export control measures based on high-end chip features.

RISC-V

Imperas Software updated its free riscvOVPsimPlus reference model, simulator, and test suites. “Architectural Validation test suites, while not a complete verification plan, offer the basic confirmation necessary to sustain the ecosystem of software support. We are pleased to offer the latest suites for the key ratified specifications of Vectors, Bit Manipulation, and Crypto plus the new Embedded E suite, all for free including commercial use, with riscvOVPsimPlus,” said Simon Davidmann, CEO at Imperas.

Imperas Software and Breker Verification Systems are teaming up to develop interfaces and standards to unify the functional verification design flows to enable design verification teams to improve efficiency and verification IP reuse across the complete verification process from plan to silicon prototype. “RISC-V represents an inflection point for semiconductor verification as the design freedoms provided by the open ISA means an assumption of the responsibility of the processor and system verification task,” said David Kelf, CEO at Breker Verification Systems. “In partnering with Imperas, the leaders in RISC-V processor verification, we can offer a combination of technologies and interface standards for IP and SoC testing that ensures commercial grade verification for these flexible devices right through to the end platform.”

DeepComputing and Xcalibyte released a native RISC-V development laptop for software development. It features a quad-core RISC-V processor with a companion NPU/GPU. “The ROMA native RISC-V development platform laptop demonstrates the power of collaborative culture and the potential of the RISC-V ecosystem,” said Calista Redmond, CEO of RISC-V International. “This design is a crucial bridge between development boards and RISC-V based business laptops that will be used for day-to-day work.”

Memory

CEA-Leti developed an event-driven, object-localization system that couples piezoelectric, ultrasound transducer sensors to a neuromorphic, resistive memories-based computational map. “We drew inspiration from biology to incorporate these two aspects of computation into our hardware, leveraging CEA-Leti’s state-of-the-art ultrasound sensors and resistive memory technologies,” said Elisa Vianello, senior scientist and Edge AI program coordinator at CEA-Leti. “In particular, we focused on the acoustic-based, object-localization task. Owls efficiently solve this problem and thus we extrapolated their computational principles into our system.”

“Our system, which could have future use in sensor-fusion applications, mimics the owl’s extremely energy- efficient prey-capture mechanism, which is preceded by combined auditory and visual search,” added Filippo Moro, of CEA-Leti. “The ultralow power consumption auditory search is always active and when a specific auditory neuron fires, the owl has the information it needs to start the visual search, which is more precise but more costly in terms of energy consumption.”

Brite Semiconductor introduced two new technologies for high-speed DDR PHYs. The first, Zero-Latency technology, adopts two optional and unique sampling methods for data transfer on the read data path, which aims to minimize latency and save silicon area. The second, True-Adaptive technology, always tracks the voltage temperature in the chip, the variation in the round-trip delay between the chip and the memory, and the skew of the read DQ/DQS, choosing an appropriate time to compensate. Users only need to train once after power on, and then the PHY will track and compensate automatically.

SiliconIntervention was granted a patent in the U.S. for a multiport memory with analog port. “An example use case is one where the analog port functions in read only mode and a digital port acts as a write only port, which allows data in the core memory to be applied to an analog signal while a digital port accesses the core memory for rapid storage of data,” said Martin Mallinson, SiliconIntervention’s Founder and CSO. “A potential application of such a multiport memory is to bridge digital and analog computation and leverage the benefits of analog compute in memory. For example, this allows a digitally programmed two-port memory to derive a sum-of-products signal from analog input signals, and multiple such memories to be used in a programmable analog neural network implementing artificial intelligence functions.”

Micron Technology made its DDR5 server DRAM available for Intel and AMD servers and workstation platforms. The company said that DDR5 enables up to an 85% increase in system performance over DDR4 DRAM.

Quantum computing

Infineon Technologies and Oxford Ionics are collaborating to build high-performance and fully integrated quantum processing units (QPUs). The companies are aiming for industrial production of QPUs offering hundreds of qubits within the next five years. “The great challenge in quantum computing is scaling whilst improving performance”, said Chris Ballance, co-founder of Oxford Ionics. “There are technologies that can be fabricated at scale but don’t perform, and there are technologies that perform but don’t scale. Our electronic control is uniquely placed to do both. Working with Infineon and its mature and flexible semiconductor process, allows us to speed up the accessibility of a commercial QPU. Due to our market-leading error rates, these processors need dramatically fewer qubits to solve useful problems than other technologies.” The first Oxford Ionics devices will be cloud accessible by the end of 2022.

The National Institute of Standards and Technology (NIST) selected the first four encryption methods that will be part of a post-quantum cryptographic standard. The four quantum-resistant algorithms rely on math problems that both conventional and quantum computers should have difficulty solving. For general encryption, used protect information exchanged across a public network, NIST selected the CRYSTALS-Kyber algorithm. Among its advantages are comparatively small encryption keys that two parties can exchange easily, as well as its speed of operation. For digital signatures, used for identity authentication, NIST selected the three algorithms CRYSTALS-Dilithium, FALCON, and SPHINCS+. Reviewers noted the high efficiency of the first two, and NIST recommends CRYSTALS-Dilithium as the primary algorithm, with FALCON for applications that need smaller signatures than Dilithium can provide. The third, SPHINCS+, is somewhat larger and slower than the other two, but it is valuable as a backup as it is based on a different math approach than the other selections. Three of the selected algorithms are based on a family of math problems called structured lattices, while SPHINCS+ uses hash functions.  Four additional algorithms are under consideration for inclusion, and the standard is expected to be finalized in about two years.

Want to learn more about programming quantum computers, but not sure where to start? Los Alamos National Laboratory published a beginner’s guide that introduces quantum algorithms and their implementation on existing hardware. “Writing quantum algorithms is radically different from writing classical computing programs and requires some understanding of quantum principles and the mathematics behind them,” said Andrey Y. Lokhov, a scientist at Los Alamos National Laboratory and lead author of the guide. “Our guide helps quantum programmers get started in the field, which is bound to grow as more and more quantum computers with more and more qubits become commonplace.”

Read more

Find more of the week’s news at Manufacturing, Test and Auto, Security, Pervasive Computing.

The burden for ensuring IC reliability is shifting left, in the latest Systems & Design newsletter. Other stories highlight why getting hardware-dependent software right is critical and how the talent crunch is driving EDA to embrace big data.

Find out if analog can make a comeback in the latest Low Power-High Performance newsletter. Plus, read why thermal issues in DRAM are reaching a crisis point and whether the IP industry is ready to undergo a transformation.



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