More Test Needed For Integrated IP

By Ann Steffora Mutschler
As the use and reuse of design IPs and cores has reached approximately 70% of the content of an SoC, the need for both pre- and post-silicon test has increased.

On the pre-silicon side, test comes in the form of verification IP. Driving the addition of more strenuous test approaches on this side is a combination of forces that impact design, noted Tom Hackett, product marketing director for verification IP at Cadence, “and some of them never change because we’re always dealing with something new. Process technology keeps evolving which is a constant.”

As a result of ever-changing design requirement, the verification IP business has grown significantly over the past several years.

Cadence aims to provide VIP (verification IP) early—usually before a new spec has been ratified, he said. “We work with about 20 different standards organizations so that we can provide these verification IP components, which are like very sophisticated models with a lot of built-in checking, to the early developers. Those are the companies that are behind the new standard and there’s always maybe a half-dozen that are really driving it.”

The idea is to work with the early standard adopters as they are getting to the last stages of the spec refinement since they are already making bets about how the spec will shake out and they are already doing their prototype designs. VIP gives the design engineers a second opinion on what that spec really says.

Hackett observed that over time [see diagram below] there has been a constant rate of change in developing the foundation interface standards that pretty much everything is built on today. “Things have been steadily growing — first it was, ‘OK, let’s have a special mobile branch, then a graphics branch, etc.’ and what really struck me is that just in the past couple of years there has been a big proliferation of specialized interfaces. What’s driving that is probably the whole mobile thing but it wasn’t just in that DRAM standard family there’s also a new SPL in PCI-Express and in a different way in the AMBA protocols from ARM.”

Evolution of the DDR memory interface standard (Source: Cadence)

“I’m convinced that what’s really driving the growth in [the VIP market] is that there is so much newness, and the rate of change has ramped up so much that people really have no choice to make a quality design they have to reach out to do more pre-silicon verification,” he said.

The manufacturing test front
Then, on the manufacturing test side, when it comes to IP, it’s all about how to test the IP once it is in the design. How is it dealt with from both a debug and a manufacturing test point of view? “This is a growing problem. The amount of IP, both internal and third party IP, is growing quite rapidly to meet the shrinking product cycles,” said Stephen Pateras, product marketing director, silicon test solutions at Mentor Graphics. “But the issue is dealing with all of this stuff in a timely manner, and the fact that each of these pieces of IP has different interfaces, different test requirements, there are a couple of major areas that are becoming important to deal with all of this various IP.”

One is integrating it and having a way of being able to quickly understand and integrate a piece of IP from a third party from a test and a debug point of view. This is where the new IEEE 1687 iJTAG standard (now on ballot) comes in, which is all about creating a standard way of describing the periphery of the IP so you can integrate it using a standard infrastructure, he said.

“If I get a piece of IP from a third party, and especially if I have dozens or hundreds of these IPs, how do I ensure that I can access them correctly, that they are properly tested, and that I can debug them once they are in my SoC? The standard defines a standard way of describing the interfaces of the IP and a standard way of describing procedures to use the IP. Once you have a standard, you can automate the process. You can automate integrating them, hooking them up, verifying them, creating testbenches, be able to take those patterns and merge them together at the top level of the chip, and re-sequence them so they can be applied in an automated way,” Pateras continued.

Both Mentor Graphics and Synopsys recently released tools in this space, as well as in the area of test efficiency and test portability, which is garnering significant user interest, both companies asserted.

Robert Ruiz, senior product marketing manager for test automation products at Synopsys, observed that overall, there is more thinking about SoC test before actual design may take place, which may mean the market is maturing a bit. “One of the trends on SoC test that we’ve seen with our largest customers who have sufficient resources is they’ve created their own ad hoc manner to do hierarchical test or a core-level test. There is planning that has to be thought about up front because typically on very large designs an entire subsystem is signed off to make sure timing is met, placement is met and these days, test has to be met also. You can think of a subsystem of an IP within a company. Maybe it’s only for one design, maybe it will be used multiple times. At our largest users that have the resources, they’ve developed their own means of hierarchical test, and we are seeing this trend of more adoption for both the cores and the IP associated with those SoCs.”

Sandeep Kaushik, senior product marketing manager for embedded test and repair at Synopsys agreed. “Definitely, as SoC complexity is increasing, there is a greater need for how to plan it from the test perspective—how to integrate different components or IPs or the building blocks of the design at the SoC level from the test perspective. Another aspect, which is related to the heterogeneity of different IP and cores, is that there could be multiple providers of those IP and cores.”

This also adds to the challenge in terms of how those IP or cores would be integrated within the SoC as they are coming from different suppliers, they have different interfaces which further can complicate the problem.

Even with the challenges of IP integration, the awareness level for pre-silicon and manufacturing test is strong; vendors have already worked on tools to address these challenges very recently with more to come. As the next wave of IP integration issues becomes clear, the technologies will follow.