How to characterize PCIe 5.0 PHY designs to avoid issues such as signal integrity and reliability prior to manufacturing.
PCI Express (PCIe) 5.0 silicon characterization across process, voltage, and temperature variations, is necessary for accelerating SoC designs. To measure key qualifying parameters, designers and test engineers must have a good understanding of the PCIe 5.0 base electrical specification and know the physical layer’s design architecture and features for accurate characterization of 32GT/s PHY performance across worst-case channels. By selecting the appropriate test equipment and setting up the right test environment, PCIe 5.0 design performance can be successfully verified in silicon prior to high-volume production. This white paper explains how to characterize PCIe 5.0 PHY designs to avoid issues such as signal integrity and reliability prior to manufacturing. It is common for equipment vendors to not have software suites available for electrical parameters until after the release of the 1.0 specification. This creates a challenge for IP vendors to test the electrical parameters as per the specification without the support of test vendors’ automated software suites. This whitepaper also describes Synopsys’ post processing techniques for testing the following key transmitter parameters at 32 GT/s: 1. Jitter 2. Spread Spectrum Clocking (SSC).
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