The Bigger Picture

Simulation and validation of the power delivery network requires a global view.


By Aveek Sarkar
IC power consumption is dependent on its supply voltage. To reduce power consumption, and heat dissipation, IC designers strive to design for lower supply voltages. But the threshold voltage that controls switching in digital CMOS devices hasn’t scaled accordingly from reliability and other considerations.

As the supply voltage reduces down close to the threshold voltage of the MOS device, the available noise margin for proper functionality unfortunately shrinks. In addition, the difference between the supply voltage and the threshold voltage must be maintained to control the amount of current flowing in the IC’s standby mode because of sub-threshold leakage. Ensuring proper device functionality and controlling leakage current depends on the supply voltage being well regulated, especially at reduced levels, such as at 800mV for example.

The path of power from the supply to a device on an IC is very complex. The flow originates from the supply source, such as a battery or a regulator, then passes through the traces on a PCB, then to the package, where it eventually flows into the IC itself by passing through the package routes. When it reaches the IC, power flows through the metal and via interconnects before ultimately reaching the switching transistors. These conduction pathways make up the many elements of a system power delivery network (PDN).

However, to ensure a reliable supply of power and maintain stable voltage levels at the transistors, the entire system PDN must be validated and optimized. For instance, package designers require an accurate electrical model of the chip, capturing varying switching currents and parasitics, when validating the package PDN structure.

Simulating a system PDN prior to manufacturing helps ensure that the power supplying the devices on an IC is reliable and well regulated. This typically concerns both high-performance and low-power designs. For instance, in high performance designs with high clock rates and faster I/O interfaces the tolerance for jitter (variations in the arrival rate of the signal) is considerably reduced, affecting reliable and predictable signal transfer between ICs. Low-power designs also are running at 1+GHz but with reduced supply voltage levels. This means they will have much higher susceptibility to PDN noise, impacting timing and functionality of the design.

One way to address the complexity of global PDN verification is to use models like CPM, or chip power model, that capture both parasitics and activity information for the die. Parasitic information enables impedance analysis of the system PDN, while activity data enables DC and time-domain simulations. Activity on the chip can be generated using VCD and/or vectorless techniques that consider system resonance among other effects.

By using a design methodology that delivers an accurate electrical model of the chip and considers the impact on dynamic voltage noise from on-die switching scenarios with a system-level focus, the designers will have more flexibility in optimizing, validating, and testing chip-package-PCB designs.

–Aveek Sarkar is vice president of support and product engineering at Apache Design, a subsidiary of ANSYS.

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