The Changing IP Ecosystem

Can the smaller IP providers keep up and afford the requirements of delivering what is needed for 20nm and below?


Is a larger IP company better suited to deliver what users need – from hardware to software to PDKs and reference designs – with larger and more diverse teams to draw upon, as well as deep foundry relationships? Or does it pay to small, quick and nimble?

The answer to that question appears to be playing out in real time. As design complexity has increased, so has the reluctance by big chipmakers to bet the farm on smaller providers—at least at the most advanced process geometries.

“The notion that a chip designer could source seven different pieces of IP from seven different smaller IP providers and integrate them all into one 28nm or 20 or 16 finFET kind of design – that’s much more problematic and challenging than trying to do it at, say, 65nm,” said Steve Roddy, Xtensa product line group director at Cadence. “A single provider brings to the table a whole portfolio of IP with a consistent method of delivery with a consistency of implementation. Having integration-ready commonality is a useful thing. It can be physical and software layer APIs, it can be metal stacks and bump pitches that are homogenized, it can be characterization reports that are consistently written on physical IP so that you can look at the characterization of a PCI and a DDR and a MIPI PHY and see in one place, here’s the sensitivity to sheet row resistance and therefore I can figure out whether or not this fab is going to be able to stay within the manufacturing tolerances, and I can compute my yields.”

Roddy noted that more advanced and complex nodes vary more over time than some of the earlier nodes did. “Even now, is 28nm stable or are there changes afoot in terms of design kits and PDKs and what are the most favored process variations, etc.? It’s been several years that people have had 28nm. It’s still not locked and loaded and ready to go, so there’s some drift there.”

The situation is even more unstable at 16/14nm and 10nm. Moreover, because of the investment in time and effort, foundries want to limit the number of EDA partners they have while working with only one or two lead-edge customers.

“A particular fab wants to get business from that particular customer – a big chip company that’s going to do 200 million units of some apps processor or an OEM that’s going to do it,” Roddy said. “And they are going to bet the farm on that one lead customer, and then tweak things – whether it be in design rules or process controls – in a way that satisfies that customer bringing up that high volume part, shaking out the line and so forth. You’re unlikely as a foundry to want to engage with seven smaller IP vendors on specialty individual cores and deal with seven companies to say, ‘I tweaked the rule deck or PDK, your models and layout need to be changed. I’ll quickly respin that test chip for you in order to get you the updated silicon.’ You’d rather deal with one partner rather than seven. It’s just the nature of things as a fab. You don’t want to have to deal with that much complexity.”

So if the ecosystem had to work closely together before, it has to work even more closely at the most advanced nodes.

“It’s earlier and it’s basically the combination of the design tools, the technology parameters that come from the foundry, and then the design expertise that the designers are providing,” said Johannes Stahl, director of product marketing for system-level solutions at Synopsys. “It’s a very close collaboration and, of course, like in the semiconductor world, fewer and fewer companies can do the big chips. In the IP world, fewer and fewer providers can afford this type of collaboration and get the access and the ability to do it.”

What this means for the IP provider landscape is that for the advanced technology nodes, the number of providers will be shrinking, he said. “The supply chain will organize in the very same way as the semis will organize—fewer companies can do the complex things and fewer IP providers can supply to the lowest, most advanced nodes. Then, there will be a number of nodes – like 28nm and above, where there will be design starts that have a lesser volume, not as critical, where more players can still be active.”

This also supports the notion of 28nm having a particularly long life.

“It’s a pure game of the cost involved for any given node and the requirement of the market to either have extremely high volume or not being able to demonstrate the volumes and living with a less aggressive node,” Stahl explained.

For smaller IP providers, there is a balancing act between how many resources are put toward IP development versus integration services that needs to come along with the IP.

Fabless IDM business model?
Given the changes afoot, does this mean the industry is leaning back toward a ‘fabless IDM” business model? Jean-Marie Brunet, product marketing director for DFM and Place-and-Route Integration at Mentor Graphics, observed that for the leading-edge semiconductor companies in the most demanding markets, the pendulum is indeed swinging back toward an integrated model where more of these fabless companies are developing IP internally. “This is how they maintain their competitive advantage and achieve the highest levels of optimization within their designs.

“Doing those IPs and validating that those IPs, at a hard IP level, will be integrated correctly within the company is a lot of work. There’s a lot of process knowledge that is built into this and density, coloring, litho-type of knowledge and contextual-type of knowledge. It makes a big difference for a company that understands that. That process knowledge is what enables the best optimization in the design and allows that company to differentiate themselves.”

IP shops vs. IP factories
Things are getting more challenging for the smaller IP companies in other ways, too. “A lot of the IP shops that were looking at bootstrapping their way into the IP business are going to be prohibited from being able to do a thorough job and get access to some of these things,” said Patrick Soheili, vice president and general manager for IP Solutions at eSilicon. “There’s just way too much risk involved with PDK 0.5 or with the number of tools that you need or the farms that you need in order to do that validations, simulations and characterizations on the back—or the type of scopes that you need to do the complete testing.”

He explained that sometimes, “those IP shops will try to find a customer first to sponsor all of the work. That’s not easy to do because they look at them and say, ‘Hmmm, this is a small guy. Maybe he’s not going to be in business a couple of years from now, let alone me trusting my next generation products to him.’ But those guys would like to use a fabless guy or a potential customer’s infrastructure or tools or scopes or labs to reduce some of it own overhead and costs. This was a lot easier to do at 28, 40 and 65nm than it will be at 20, 16 and 14nm.”

While some of the challenges may outweigh the benefits for some smaller IP providers to play the game, the semiconductor suppliers are ultimately calling the shots once again, as more integrated approaches appear to be their ace in the hole.

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