The Chiplet Option

All of the leading chipmakers, foundries and OSATs are now working with some sort of advanced packaging. The next step is to add some consistency to those efforts to be able to assemble chips much more quickly and inexpensively.

DARPA has been promoting chiplets as the best way to solve this problem, and for the military, this is a pretty logical choice. With a push toward heterogeneity in computing, chiplets are a way of consolidating chips into packages where the entire supply chain can be traced much more easily than with IP blocks in an SoC. Chiplets also are a way of assembling an integrated chip more quickly because the chiplets themselves can be tested, fully characterized and packaged together like subsystems.

Whether this works commercially remains to be seen. So far, only Marvell is utilizing a menu type of approach based upon its MoChi interconnect infrastructure. The company uses that approach internally to develop its own products, as well as externally for customers. But the real opportunity for chipmakers is to be able to source standardized chiplets from multiple vendors and assemble them quickly for final validation and test. In theory, this should sharply reduce the time spent in verification and debug, which today can consume upwards of 70% of the NRE in chip design.

Chiplets add an element of predictability into the design process. With a flexible interconnect infrastructure, design teams in theory should be able to choose exactly the right sized memories, SerDes, I/O and processor speeds and accelerators, all of which can be pre-verified and tested. So rather than buying pre-integrated IP subsystems, in effect they would be able to build their own. And given the fact that not everything will be required to be at the same process node, they should be able to mix and match those chiplets based upon the end device requirements.

Nothing ever goes according to plan, of course. As with all complex chips or packages, there will always be some debug, additional verification and validation. And chipmakers still will be required to develop their own IP, without which there would be no differentiation. But the real advantage of this approach is it allows the verification, validation and debug to be split across many vendors rather than just one, so that chipmakers can spend more time being creative with their own differentiation circuitry or software or whatever they’re trying to build into systems.

Chiplets aren’t the only way to get this done, of course. There are various packaging methods ranging from various types of fan-outs to 2.5D to integrate entire chips, which greatly improve throughput and performance over an SoC at the latest process node. The tradeoff there is cost, because the interposer layer is expensive, which is why Samsung and Intel have developed low-cost bridges for their multi-die packages. And monolithic 3D integration remains the ultimate goal for cutting cost and improving performance, because through-silicon vias can go through the center of chips to improve throughput and the amount of power required to move data. The problem there is heat, which is difficult to dissipate in a monolithic package.

Chiplets may prove to be something of a middle ground in this race, and a number of major chipmakers acknowledge privately they are exploring this option. They are especially looking at alternatives after 7/5nm, when existing finFET structures will run out of steam, requiring the introduction of some type of gate-all-around FET, new materials for interconnects and contacts, not to mention multi-patterning for EUV lithography.

To make all of this work will require an enormous amount of effort. An infrastructure needs to be created to sell and distribute these components, and there needs to be guaranteed sourcing, ways of handling chiplets without damaging them, and methods established for testing known good chiplets. And even then, there are no guarantees this will ever become a serious approach for many companies. But what has changed is more companies are now looking at this option, and that alone is significant.