The Convergence Of Advanced Packaging And SMT

One statement is almost always true in the electronics industry: smaller is better. The relentless demand for electronic systems that pack more computing power and functionality into less space has driven the development of new processes and designs since the invention of the integrated circuit. In recent years that drive has taken a new direction, literally, as manufacturers have discovered that it is easier to go vertical than to continue to shrink laterally, in only two dimensions. Now they are building skyscrapers where once they laid out neat neighborhoods of single-story ranch houses. The need to provide connections among components presents a unique challenge as the number of connections increases and their sizes decrease.

For most of the industry’s history the worlds of device manufacturing and system assembly were largely separate. Device manufacturers fabricated chips and packaged them to provide protection and connections to the outside world. System assemblers mounted packaged devices, usually with surface mount technology (SMT), on printed circuit boards to provide communication, power, and more. As new designs incorporate more powerful chips and sometimes multiple chips in a single package, the number of connections needed, both within the chip and to the outside world, has multiplied. To provide these connections manufacturers have adopted advanced packaging (AP) processes, many of which adapt front-end-like manufacturing processes to traditionally back-end packaging applications. As demand grows for more, smaller, denser connections, and those connections migrate inside the package, the conventional line between packaging and assembly has blurred.

Nowhere is this more evident than in the inspection and measurement capabilities needed to detect defects and control advanced packaging and assembly processes. Connections for SMT-based assembly are typically larger than 100µm (for comparison, a human hair is about 80µm). Connecting pathways within a chip are typically smaller than 10µm, sometimes a thousand times smaller. The size range between front-end manufacturing and back-end assembly, from 10-100µm, where advanced packaging and SMT are converging, is sometimes called the mid-end. In this range manufacturers need a unique combination of resolution, accuracy and speed that is not available from existing optical inspection technologies. For example, the bumps and pillars that provide vertical connections between stacked chips range in size from about 100 µm for a mature C4 process to as small as 10µm for the most advanced µ-pillars. And there may be tens of millions of bumps on a wafer, each needing inspection and measurement. Many solutions developed for front-end applications have the needed resolution but are too slow, while systems developed to inspect PCBs may be fast enough but lacking in resolution.

Figure 1: Bump sizes and pitches are decreasing and the number of bumps per die is increasing. The NanoResolution MRS sensor can support most current and next generation processes. (Source: Dow Chemicals)

This is precisely the opportunity our new Nano Resolution MRS sensor was designed to address. Using an innovative optical technology and sophisticated analytical algorithms it provides an unparalleled combination of speed, accuracy and resolution. The current sensor delivers 3µm lateral resolution and 50 nm vertical resolution and can potentially scale to 1.5µm lateral and 25nm vertical. It can measure both 2D and 3D dimensions in a single pass, acquiring and processing up to 75 million data points per second, fast enough to provide 100% inspection of up to twenty-five 300mm wafers per hour.

In coming additions to this blog we will look more closely at MRS technology and its applications, including explanations of how the technology works, where it is being used (memory modules, micro-LEDs, and more), and some of its unique capabilities like its ability to characterize shiny surfaces – solder balls, anyone?