The Enterprise Effect

Data centers are now driving sub-40nm designs for network control chips; speed plus demand for reduced power are forcing changes across the networking spectrum.

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By Pallab Chatterjee
In the enterprise it’s all about speed and power—as in more speed and less power—and those changes are forcing shifts in the chip architectures as well as the processes used to develop those chips.

At the Linley Data Center Conference the next generation of network control chips were discussed. The keys for the new networks are 10G data lanes to be used with 10G/40G and 100G applications. For 100G the alternate configuration from 10 lanes of 10G was 4 lanes of 25Gb/s also being designed with 40nm.

The 40nm processes give the advantage of the data speed that was needed, plus power savings that are required to keep the reliability of the die and package. The trend is that these high-speed switches need to be available not as single PHYs, but as duals and quads. The 40nm node allows for target power at about 3W for these parts, which will enable 24- and 48-channel switch products.

The PHY that is being provided by most of the vendors can, with the 40nm process, support security data processing. The architecture for many of the high-throughput data systems includes local data analysis, decryption, policy and authentication testing off the early data bus just after the transceivers. These application processors can be on the same die or separate die from the PHY.

In applications where there are separate server processor chips, the trend is toward 32nm processes with multicore configurations. Intel is offering 6- and 10-core products under the Westmere architecture. For the upcoming Sandy Bridge architectures, they are featuring 8 and 12 cores using the 32nm process. On the server processor side, there also are 32nm products from AMD using the new “Bulldozer” architecture. Rounding out the server side there are also new cores from ARM with the Cortex A-15.

For dedicated application processors, a number of multicore processors are now available using 40nm processes. These include the 16-core Octeon from Cavium Networks, the 8-core QorIQ from Freescale, the 4-core ACP3448 from LSI, and the 8-core XLP family of processors from Netlogic Micro. Also in this space is the Netronome NFP-3240, which is a 40-core 40Gbps flow processor that is a co-processor to the Xeon main processor for network traffic handling.

One of the power/performance drivers is the security aspects of the networks. The Federal Information Processing Standards (FIPS) 140 is focused on cryptography and security systems, not on items such as firewalls, Web filters, spam and virus protection, or content and flow control. The cryptographic modules are constantly increasing in complexity of their algorithms and degree of touch of the data.