The Good Kind Of Regulation

This month I’m taking a page from the Editor’s book, (actually the title for the article here came from Ed Sperling) and I decided that the above title would be fitting for this article. Last September we took a look at IBM’s presentations on their POWER8 processor from HotChips. One of the multiple new interesting aspects of this design was the use of many on-chip integrated voltage regulator modules (iVRMs) to help improve the energy-efficiency of the POWER8 design. At the time, on-chip inductors were mentioned, but based on more recent presentations given last month at ISSCC, it appears that those on-chip inductors are being used for energy efficient clock-circuitry and that IBM has another clever solution for their iVRMs.

Figure 1. DVFS Benefits vs. DFS [1]

Figure 1 shows why IBM is interested in having a fine granularity control over the on-chip voltage. As was shown here, the POWER8 is a 12-core chip and each core can be individually controlled for frequency and voltage. IBM describes the processor as being comprised of 12 “chiplets,” and each chiplet actually has 4 regulated domains for a total of 48 domains across the 12 chiplets. Having to run a core or chiplet at a higher voltage level, because it’s sharing its domain with a neighboring chiplet that wants to run at a higher frequency, leads to wasted energy for the chiplet that is running at a lower frequency (and could also drop its voltage). Figure 1 clearly shows this savings in lower performance modes when using dynamic voltage and frequency scaling (DVFS) vs a simpler dynamic frequency scaling (DFS) scheme.

Figure 2. POWER8 Chiplet with UREGs [2]

Figure 2 shows the layout for the chiplet with four voltage regulator controllers (VREGCs) and the distributed micro integrated voltage regulators (referred to as UREGs). Each VREGC controls its associated UREGs in its domain. In the diagram, the UREGs are color coded to match the outline color of the corresponding VREGC. Overall, there are a total of 1764 UREGs per chip. One novel item about this approach is that the VREGCs communicate with the UREGs by sending a digital code telling the UREGs to either increase or decrease the controlled voltage. Vdd_core can be programmed to a nominal 6.25mV resolution.

If you look closely at the chiplet in Figure 2, you’ll notice that the UREGs divide the chiplet into 5 columns where the input voltage grids and power header (PFETs) are also placed.

Figure 3. Basic UREG Structure [1]

Figure 3 shows a simplified schematic of the UREG. The comparator in this circuit has a sub-nanosecond response time and is used to generate control pulses (shown as M0G) to regulate the voltage. IBM claims that with Vdd_in=1.1V and 0.61<=Vdd_core<=1.05V, the load regulation error is less than 3mV. Also with Vdd_in at 1.1V, the iVRM at peak power efficiency is claimed to deliver 11.9A at Vdd_core=1.03V for an incredible power density of 34.5W/mm².

With all of this fine-grained controllability on the chip, some real compute horsepower is necessary to run the algorithms that determine how to respond to workload variations and other chip environment variables. IBM hasn’t skimped here either, using an on-chip controller (OCC) that consists of a full POWERPC 405 core with 512KB of its own private memory. The new power controlling features of the POWER8 processor looks like they will help keep IBM very competitive in the server and performance computing businesses.

[1] 5.1: POWER8TM: A 12-Core Server-Class Processor in 22nm SOI with 7.6Tb/s Off-Chip Bandwidth, E. Fluhr, et. al., ISSCC 2014.

[2] 5.2: Distributed System of Digitally-Controlled Microregulators Enabling Per-Core DVFS for the POWER8TM, Z. Toprak-Deniz, et. al., ISSCC 2014.