The Great Divide

The design world has split between those chasing the most advanced process nodes and those lingering at older ones, creating uncertainty across the supply chain.


By Ed Sperling
One size no longer fits all, and that’s causing consternation across the supply chain from established EDA vendors to point tool developers all the way up to the largest chipmakers.

While the overall number of design starts for SoCs really hasn’t changed much, despite a drop in the number of companies working at the most advanced process nodes, what has changed significantly is how companies are getting chips out the door, what process node they’re using and how they view the future of design. And for EDA companies, which get the biggest return on investment when they can build tools that automate processes and tasks for the multitude of engineers rather than just a few, this puts them into a quandary. Do they develop tools for the few that are willing to pay for automating some of the complexity at advanced designs, or do they look at alternative approaches.

The answer for the Big Three—Mentor Graphics, Synopsys and Cadence—has been to cater to the most advanced customers while also spreading into adjacent markets for incremental growth. The question for them is whether the adjacent markets will provide enough growth to warrant the investment.

For point-tool makers, the question is what kinds of problems need to be solved and who’s willing to pay for a solution. And at the most advanced process nodes, the question among chipmakers is whether they’ll be forced to develop their own tools at greatly added cost, whether the tools will be available from commercial vendors as regularly as in the past, or whether they can get buy with existing tools from older nodes.

Cause and effect
At the most fundamental level, there is a schism in the design community between those looking to reach the most advanced node—those who make memory chips, smart phone SoCs, GPUs and CPUs—and those who can live with improvements at older nodes ranging from 130nm to 180nm where tweaks can improve performance and/or lower power consumption.

One of the best real-world measurements of this trend is in the standard IP sold by companies like Synopsys and Virage Logic. John Koeter, vice president of marketing for Synopsys’ IP and Systems, said the number of SoCs with one or more processors is staying constant at about 3,500 design starts and expected to increase to 3,700 in the next few years.

“From a raw number standpoint, the TAM (total available market) is the same or growing,” said Koeter. “But what’s also going on is people are staying longer at any process node. We track 1,000 to 1,500 IP requests, and of those about 43% of the demand is at 65nm and 35% is at 45nm.”

So what about the other 22%? “As an IP provider, we’re being asked to re-optimize IP at older nodes,” he said. “In some cases it’s how you enable a lower-cost system. We’re seeing a lot of demand at 110nm and 130nm in Asia/Pacific for devices fitted with the latest standards like USB 3.0 for low-cost applications.”

Hedging bets
Evidence of this change is everywhere in EDA these days. All of the Big Three are pushing into adjacent markets. Mentor’s push into DFM with Calibre is paying off big for the company, despite the fact that when the company began going down that path it was greeted with widespread skepticism. Mentor also has pushed into other areas such as mechanical analysis and more recently PCB design.

Synopsys, meanwhile, has focused on IP and software prototyping, so that software can be developed in conjunction with the hardware. The moves are more in line with Synopsys’ overall flow, but its push into power analysis with Eclypse and more recently into high-level synthesis and FPGA tools are a step outside the company’s traditional borders.

Cadence, in contrast, has pushed heavily into a software-first approach with its EDA 360, an idea that has been circulated around EDA for years but which is being taken seriously now in part because of the complexity and cost of developing chips at advanced nodes. The company also just announced plans to buy Denali, which makes modeling IP.

“About 70% of a chip is re-use,” said Vishal Kapoor, vice president of product management at Cadence. “The challenge is integration. So far we’ve made sure it is compliant, but what we need to develop are tools that are built with a focus that ranges from creation to integration. And then we have to make it so it can be integrated into an SoC.”

Kapoor said IP is what’s expected from EDA vendors. But he said the rest of the world is software-driven, with the application being the most important. “If the hardware guys do not present differentiated pieces of hardware we will see commoditization of the hardware. The consumerization trend is forcing us to think about getting the most out of hardware.”

But even IP vendors aren’t just IP vendors anymore. Virage Logic, which started out making logic and memory IP, is now extending into other areas of the design such as built-in test.

“It’s not architecture first and then the system,” said Yervant Zorian, Virage’s chief scientist. “It’s building blocks coming together. In the past it was build everything together and then think about testing. It’s not an add-on. It’s now an integrated part of the smallest units that you’re building.” He noted this approach first began with memory more than a decade ago, but it is now being implemented into almost everything.

Thinking in 3D and other technologies
Perhaps the biggest changes will come by way of packaging and three-dimensional design. That will allow chipmakers to keep some of the old design, particularly the analog blocks, while leveraging the digital components that do benefit from Moore’s Law. Analog has never fit into that equation.

“What we’re seeing is the impact of system in package,” said Gary Smith, president of Gary Smith EDA. “You lag on analog and try to keep up in digital. What’s interesting is we probably have all the technology you need to switch already. In 3D, we’ve got most of the problems already solved. The next step is to get the cost out with volume.”

One of the interesting things about 3D technology is it allows companies to focus on a smaller piece of the overall development and to utilize the most advanced process nodes in addition to less advanced ones. That drives down the cost of development significantly and brings companies that have abandoned Moore’s Law because of cost back into the two-year digital process cycle. Processors and certain types of memory can still progress to the next node while analog and I/O may persist at older nodes for years and still gain performance and power consumption benefits through shorter wires and through-silicon vias.

Smith says 10% to 20% of the chip still needs to be created each time a new chip is introduced to remain competitive, but even if that number remains constant some of that development may be on the analog rather than the digital side. It also may be the software, or it could be the hardware optimized for the software or the software optimized for the hardware. Or it could be a faster I/O channel and a virtualized chip environment.

Smith, for one, believes the big innovations will be in packaging and stacking. He also believes that CMOS as we know it will run out of steam over the next few process nodes, and that what will make other substrate materials more cost-effective will be the same volume production that has kept Moore’s Law viable since it was first introduced in 1965.

FPGAs have taken an early lead in this arena. Actel’s SmartFusion platform includes programmable analog with an FPGA. Xilinx reportedly is working on its own version of programmable analog blocks.

While it’s too early to tell which approach is the right one or exactly what path will prove most profitable for developing chips, IP and ultimately software, it is clear that a transition is under way. And while transitions are always interesting to watch, they also produce fallout in the way of winners and losers—and potentially new competitors.

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