The Impact of 3D Packaging

Lower power, but higher cost, with mixed opinions on design time and cooling options.

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With semiconductor packaging becoming a more crucial piece of the Moore’s Law roadmap, the industry is still sorting out the impact of a 3D design and packaging approach on design time, cost and power.

3D is now commonly used for high volume applications such as cell phones and SD cards, and is accomplished at the packaging step either through chip stacking or package-on-package (PoP) stacking. In a cell phone, for instance, many chip stacks can be found, most involving memory: NOR Flash, NAND Flash and Mobile DRAM. Mobile DRAM, in particular, is designed with perimeter edge bond pads similar to other chips, which is good for stacking but very different from mainstream DRAM that has bond pads along the chip centerline making it very difficult to stack. NOR, NAND and Mobile DRAM, meanwhile, typically have different die size ranges and can be stacked with all wire bond pads exposed.

“Design times for chips that are to be stacked can be significantly longer due to the complexities associated with co-design for the chips and system,” said Philip Damberg, vice president of interconnect, components and materials for Tessera’s Micro-electronics group. However, the products that drive 3D scaling, cell phones and SD cards assure large volumes and low unit costs. 3D shortens interconnects resulting in power savings and performance improvements.”

While through-silicon via (TSV) technology promises to reduce power for high-performance computing systems by dramatically reducing signal lengths and increasing bandwidth between processors and memory chips, there are also challenges. “Via placement, via reliability, managing signal integrity and thermal dissipation are enormous [challenges] but promise significant savings in power and improvements in computational performance,” reminding that Tessera pioneered TSV for image sensors and demonstrated wafer level memory stacking and is currently exploring 3D applications for applying these technologies further.

Lee Smith, vice president of laminate business development at Amkor Technology, agrees: “Form factor and time to market have really been the drivers within the mobile multimedia applications that have driven the need for 3D packaging, whether that’s stacked die or package stacking. And with the volumes that their requirements have driven, the technologies have very quickly become cost effective.”

And with standards being adopted in the industry there are multiple sources of supply, which have brought costs down, he said.

“Another benefit of stacking the key processor to the memory interface, which is operating at higher and higher speeds, is that it increases the design cycle time to basically re-use the technology now that the standards are in place. So it is possible to get a well-characterized, high-speed memory interface that’s got proven signal integrity from use in a phone and it basically becomes a plug-and-play and reduces the development cycle for new phones, which is a big cost savings,” Smith said. “By going to next-generation 3D architecture with through-silicon vias you can greatly reduce power and greatly boost performance, and eventually it can provide a cost reduction versus the cost and challenges of continuing to try to do it through scaling because we haven’t seen the benefits of scaling since probably the 90nm node. The performance advances have come from material changes in the CMOS process. As a result, when you get down to the 32 and 22nm nodes, actually, the 3D architectures can provide a cost performance versus just continuing to do things in a planar fashion.”

Still, if higher density and higher performance in a given embedded square area is not needed, “there’s no reason to stack at all because it will slightly increase the cost and will have yield impact, so you’ve got to absolutely have the need for miniaturization and performance within a certain volume,” said Jack Bogdanski, director of marketing for defense and aerospace at White Electronic Designs (WED) in Phoenix.

Bogdanski estimates that stacking the die alone only adds a few percent of cost, which makes it a non-issue. However, a big argument against stacking is thermal management. “The biggest question is always going to be how to get the heat out of it,” he said. Because of this, WED runs emulations and provides other design information to its customers on thermal management.

Another argument against stacking is the location of the bonding. For example, DRAM is typically center-row bonded when wire-bonding packaging is used, but in order to stack there must be a perimeter bond. As such, a center-row bond requires additional processing.

However, packaging supplier Vertical Circuits Inc. (VCI) said its vertical interconnect pillar technology is an alternative to through-silicon via. Vertical interconnect pillar technology does sit on the perimeter of the die, according to Yin Chang, responsible for sales and marketing for VCI.

Chang also pointed out that when using a stacked approach in terms of design, there is relatively little impact unless through-silicon via technology is used. If that is the case, there is a fundamental change in how the chip is designed, in terms of where to place the vias and how the vias affect the surrounding circuitry along with thermal concerns.

As 3D IC design and packaging technology has garnered increasing interest over the past few years, so too have industry groups. One such effort is the EMC-3D consortium, which was co-founded in 2006 by EV Group (EVG) and others create and enable the implementation of a cost-effective through-silicon via (TSV) process.

Separately, EVG also collaborates with R&D centers, including IMEC and CEA-Leti, as well as joint development partners like Brewer Science, to provide leading-edge wafer bonding and debonding capabilities – particularly to address the ultra-thin wafer handling needs for 3D ICs.

Upcoming events on 3D IC technology include a variety being held during this year’s Semicon West conference, along with a BrightSpots panel, being held July 6 to 24, with the first of its technology series focused on 3D IC.