The Importance Of Embedded In-Chip Monitoring In Advanced Node CMOS Technology

By Oliver King & Ramsay Allen

With advances in CMOS technology and the scaling of transistor channel lengths to nanometer (nm) dimensions, the density of digital circuits per unit area of silicon has increased as has the process variability of devices manufactured.

The increase in digital logic (or gate) density, which equates to an increase in power density, is a major contributor to the heating of semiconductor devices manufactured on advanced node CMOS technologies. In-chip temperature monitoring is used for performance optimization, an example being Dynamic Voltage and Frequency Scaling (DVFS) where, depending on the thermal conditions, system clocks and voltage supplies can be varied to optimize either the speed of logical operations or power consumed by the device.

Process induced variations in circuit delays have begun to significantly adversely affect chip performance and power consumption. A statistical analysis of each device would show a process variability, or spread, that when compared to historical CMOS technologies is wider (worse) for advanced technology nodes. To address this, manufacturers have to design their Systems-on-Chip (SoC) to over-compensate for unwanted variability arising from manufacturing processes.

Increased logic gate density, increased track and via impedances and process variability has led to significant voltage (IR) drops across advanced node devices. Together with an increasingly noisy environment, the need to monitor core supplies in-chip has become desirable to ensure that operating conditions are acceptable to the complex systems in today’s devices.

Moortec’s embedded monitoring subsystem includes a high precision low power junction Temperature Sensor that has been developed to be embedded into ASIC designs. It can be used for a number of different applications including Dynamic Frequency and Voltage Scaling (DVFS), device lifetime enhancement, device characterization and thermal profiling.

It also features a Process Monitor which provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices. The Process Monitor can be used to enable continuous DVFS optimization systems, monitor manufacturing variability across chip, gate delay measurements, critical path analysis, critical voltage analysis and also monitor silicon ‘ageing’.

Lastly, the Voltage Monitor is a low power self-contained IP block specially designed to monitor voltage levels within the core logic voltage domains and provide accurate IR drop analysis. The measurement range is customized to suit each technology. The monitor IP can also monitor analogue (IO) supply domains and is also well-suited to monitoring supply droops and perturbations.

The subsystem also includes the sophisticated Process, Voltage and Temperature (PVT) Controller with AMBA APB interfacing, which supports multiple monitor instances, statistics gathering, a production test access port as well as other compelling features.

The PVT monitoring subsystem IP is designed to optimize performance in today’s cutting-edge technologies, solving the problems that come about through scaling of devices. Applications include data center & enterprise, automotive, mobile, IoT, consumer and telecommunications.

In-chip monitoring has become a vital factor in the design and performance optimization of small-geometry designs. Since 2010, Moortec has brought to market a highly featured embedded PVT sensing fabric for use in-chip within advanced node CMOS technologies from 40nm down to 7nm.

Make sure to check out upcoming webinars on Why Use Embedded In-Chip Montiroing. The webinar will take place on Wednesday, Dec. 6, at 6:00 p.m. GMT (10 a.m. PST) for the U.S and Europe (register here) and again on Thursday, Dec. 7, at 8:00 a.m. GMT (4 p.m. CST) for China, Taiwan, South Korea (register here).

Ramsay Allen is vice president of marketing at Moortec Semiconductor.