The Week In Review: Design

ARM to acquire Duolog; Cadence offers USB 3.0 host controller IP; Synopsys rolls out DesignWare ARC processors optimized for low-power embedded DSP apps; Yatin Trivedi awarded Accellera Leadership Award; Chip Path announces free access to its multi-vendor architectural FPGA and FPASSP mapping tools; Sidense embedded memory macros approved for TSMC 28nm processes; ST adopts Mentor Graphics’ Veloce 2 emulation; Synopsys DesignWare IP validated in TSMC 16-nm FinFET process; ANSYS and TowerJazz deliver power noise and reliability sign-off design kit; Learjet 85 implemented with Mentor’s electrical wiring system software.

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M&A
ARM said it is acquiring Duolog Technologies, a player in design configuration and integration technology for the semiconductor industry. ARM said this will expand its position for deploying complex system IP including debug and trace IP. Terms of the deal have not been disclosed.

Tools and IP
ARM’s Cortex A9 core is at the heart of a new secure processor from Broadcom aimed at endpoint applications such as payment terminals and devices aggregating data from Internet of Things applications.

Cadence Design Systems announced that a production proven host controller IP for USB 3.0 has been added to its IP offering. The Cadence USB 3.0 xHCI host controller IP was originally developed by Fresco Logic, a global fabless semiconductor company that develops and markets advanced connectivity solutions.

Synopsys announced availability of the DesignWare ARC EM DSP Family of processors, which includes the ARC EM5D and EM7D processors designed for low-power embedded digital signal processing applications.

Memoir Systems announced availability of its Renaissance soft memory IP for ARM Artisan physical IP targeting TSMC 16nm FinFET-Plus (16FF+) designs.

Chip Path Design Systems said its device-mapping tools and IP directory for FPGA front-end design can be accessed for no charge and paid for by credit card. Using only a web browser with no software installation required, the Chip Path portal and IP directory are freely accessible from anywhere in the world, allowing designers to design, research, compare and plug-and-play hundreds of IP blocks onto FPGA devices across multiple vendors.

Sidense Corp. announced that the its 1T-OTP macros for TSMC’s 28nm HPL, HPM and HPC processes have met all TSMC9000 Quality Management Program requirements.

ANSYS and TowerJazz have collaborated to create a foundry certified power noise analysis process design kit that includes reference flow guidelines, collateral, example test cases and flow setup guidance meant to enable analog and RF designers to produce optimized ICs faster and with confidence, minimizing cost and maximizing manufacturing yield.

Deals
STMicroelectronics said it has adopted Mentor GraphicsVeloce 2 emulation platform to boost productivity in the verification of SoC and IP-based designs.

Synopsys reported it has validated its DesignWare IP in the TSMC 16-nm FinFET process technology.

Mentor Graphics also noted that Bombardier Aerospace has implemented a complete digital development process based on Mentor technology for the Learjet 85 aircraft’s electrical distribution system.

Recognition
Accellera Systems Initiative has named board member Yatin Trivedi the recipient of its 2014 Leadership Award, which recognizes the vision, leadership and contribution to standards development, governance and promotional activities of the organization. The Award will be presented at the Design Automation Conference during the Accellera breakfast meeting, June 3.