Week In Review: Design, Low Power

Ethernet TSN IP; Synopsys and Siemens end patent battle.

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CAST debuted an IP subsystem implementing the latest IEEE standards for Time Sensitive Networking (TSN) over Ethernet. The TSN_CTRL Subsystem combines three IP cores, a time synchronizer, traffic shaper, and Ethernet MAC. It implements a hardware subsystem that operates without software assistance once programmed. The IP communicates timing information to the system, and allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements.

Synopsys and Siemens PLM settled all outstanding patent litigation between Synopsys and Mentor Graphics. The settlement includes mutual seven-year patent cross-licenses between Synopsys and Siemens, and between Synopsys and Mentor Graphics, as well as a Synopsys payment to Siemens of $65 million. The two companies also plan to collaborate on a range of EDA product interoperability projects.

Hitachi used Cadence’s JasperGold Formal Verification Platform to verify νCOSS S-zero, an industrial facilities functional safety controller that has been certified for Safety Integrity Level (SIL) 3 in accordance with the IEC 61508 functional safety standard. Hitachi also developed measures for fault avoidance to comply with SIL 4 requirements.

Cadence’s full-flow digital and signoff tools were certified for Samsung Foundry’s 7nm Low Power Plus (LPP) process technology.

What was hot at DAC this year? Technology editor Brian Bailey covered the trends and issues facing the industry on Monday, Tuesday, and Wednesday.



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