The Week In Review: Design

New verification tools; 28nm super low power; deals; robot puzzles; tech manufacturing hubs.

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Tools
Synopsys uncorked the next version of its verification tool, which includes static and formal verification, new debug capabilities, and low-power and X-propagation simulation. The company says the new tool offers up to 5X performance improvement.

Cadence rolled out a new version of its verification solution for designs using ARM’s interconnect IP, speeding up verification and analysis.

Deals
GlobalFoundries certified Cadence’s physical verification system down to 14nm. The design tools are ready, even if the lithography isn’t.

Synopsys won a deal with STMicroelectronics, which is using Synopsys’ place and route tools for all of its general-purpose and graphics processor implementations.

Cadence won a deal with Russia’s Mikron, which is using Cadence’s verification and signoff tools in its 90nm design flow. http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=031214_Mikron&CMP=home

Technology
Cadence and GlobalFoundries rolled out a test chip using an ARM Cortex-A12 processor developed on a 28nm super low power (SLP) process. What makes this announcement particularly noteworthy is that it runs at 2GHz, which is enough for many mobile applications without double patterning or any special materials.

A CUBESTORMER 3 robot based on a Samsung smartphone and an ARM9 processor is vying to break the 5.27-second world record for solving Rubik’s Cube. That leaves the robot lots of spare time. What else can it do?

The White House is launching manufacturing hubs and pushing funding for transformative infrastructure technology. Our take: This will require a lot of semiconductors.