The Week In Review: Design

FTC greenlights ON Semi/Fairchild deal; OTP memory; SSD controller; IIOT communication.



The FTC has given the go-ahead to ON Semiconductor’s acquisition of Fairchild Semiconductor. As part of the requirements, ON Semiconductor had to divest its planar insulated gate bipolar transistor business, which will be sold to Littelfuse. (Littelfuse will also pick up the transient voltage suppression diode and switching thyristor product lines for a combined $104 million in cash.) The deal has been pending since November 2015 and offers $20 per Fairchild share, approximately $2.4 billion.


Sidense demonstrated successful operation of its SHF 1T-OTP one-time programmable memory macros on TSMC’s 16FF+ and 16FFC process nodes. For 16nm implementation, Sidense is adding several enhancements to its architecture including low-voltage reads along with a differential read mode and enhanced security features.


Starblaze Technology completed a new SSD controller chip using Sonics’ NoC to integrate more than 60 cores, citing performance features, intuitive development environment, and support for standard EDA design flows. Tape out was completed in April, and volume production in TSMC’s 28HPC process technology is targeted for later this year.

Gridbee implemented Synopsys’ ARC EM6 Processor in its plug-and-play wireless communication device for industrial environments. The solution is based on medium and long range radio frequency technology (IEEE 802.15.4g SUN with both FSK and OFDM modulation) to enable communication with the machines’ network and a mesh network infrastructure and use very little power when not communicating.

Irida Labs’ imaging/vision software is now available on Cadence’s Tensilica Vision DSPs. IRIS-EnLight low-light video software enhances videos and images taken in challenging lighting conditions and slow shutter speeds, while IRIS-NoiseSweeper is targeted at image noise reduction for high-resolution still images.

Movidius will incorporate UltraSoC’s monitoring and analytics IP and tools into its next-generation low-power machine vision SoCs. The IP will be combined with Movidius’ debug technology for a chip-wide debug and communications infrastructure.

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