The Week In Review: Design

Mentor buys Valydate; Cadence optimizes for latest ARM cores; Aldec adds more rule-checking capabilities; DVCon Europe.

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M&A
Mentor acquired Valydate, provider of the VERA schematic integrity analysis tool. Founded in 2010, the Canadian company also offered signal and power integrity and static timing analysis services. Valydate’s technology will be integrated with Mentor’s Xpedition PCB design flow, though former Valydate CEO Michael Alam says it will continue to serve all EDA environments.

Tools
Aldec updated its ALINT-PRO verification tool, adding more rule-checking capabilities in response to the design subset constructs that have been recently added to SystemVerilog. The new release is able to flag typical issues including 2-valued vs 4-valued data, user-defined types, new kinds of processes and conditional statements, new expression operators, and advanced constructs to model re-usable design hierarchies. It also provides full coverage of block-level constraints for Microsemi FPGA libraries.

Cadence released a set of 7nm Rapid Adoption Kits (RAKs) for Arm’s Cortex-A75 and Cortex-A55 CPUs and the Mali-G72 GPU. Cadence’s digital and signoff tools have been configured to provide optimal PPA results using the RAKs, which include scripts, an example floorplan, and documentation for Arm’s 7nm IP libraries.

IP
PLDA launched a highly efficient many-channel DMA engine targeted at SoCs for virtualized data centers. The vDMA IP Core allows up to 2048 dynamically reconfigurable DMA channels that can be distributed among up to 512 virtual machines and supports data security and VM isolation features.

Morpho will optimize its computational photography software for Synopsys’ DesignWare EV6x Vision Processors. Morpho’s image classification technology uses deep learning algorithms to analyze visual input and automatically apply tags. On the EV6x, it targets mobile and surveillance SoCs.

Events
Registration is open for DVCon Europe 2017. The conference’s keynotes focus on sensors and automotive this year: Horst Symanzik of Bosch Sensortec will discuss growing MEMS complexity and some of the challenges faced in ASIC development for MEMS products, while Berthold Hellenthal of the Progressive Semiconductor Program at Audi AG will consider the latest design and verification challenges in the automotive space. DVCon Europe will be held Oct. 16-17 in Munich, Germany.

The agenda for Mentor’s IESF (Integrated Electrical Systems Forum) 2017 conference has been announced. Bob Lutz, a former executive at General Motors, will give a keynote speech. The event, focused on EE design issues in automotive and mil/aero systems, will be held Sept. 20 at the Inn at St John’s in Plymouth, MI.