The Week In Review: Design/IoT

5nm test chip tapeout; test tools from Synopsys and Mentor; DSP updates.


Imec and Cadence completed the first tapeout of a 5nm test chip. Using a processor design, the companies taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning.


Synopsys folded in recent acquisition Atrenta’s testability analysis into its ATPG and diagnostics technology. According to Synopsys, memory-efficient, multithreaded engines for test generation, fault simulation and diagnosis make for 10X faster run time and 25 percent fewer test patterns. Additionally, key components of Synopsys’ manufacturing test solution, are now certified for the ISO 26262 automotive functional safety standard by SGS-TÜV Saar.

Mentor Graphics released its latest DFT product, which applies local circuit modifications to reduce assignment conflicts that arise during the test pattern generation process. Mentor says the resulting improvement in pattern generation efficiency translates into significant pattern count reduction.


Cadence unveiled its latest high-performance vision/imaging DSP core, which it says offers up to 13X performance boost, with an average of 5X less energy usage on vision tasks compared to the previous generation IVP-EP imaging and video DSP. The core includes a significantly expanded and optimized Instruction Set Architecture targeting mobile, automotive, and IoT.

CEVA introduced a real-time neural network software framework for machine learning in low-power embedded systems. According to CEVA, when combined with its DSP, the framework allowed embedded systems to perform deep learning tasks 3x faster than leading GPU-based systems while consuming 30x less power and requiring 15x less memory bandwidth.

Arasan uncorked its UFS 2.1 Host Controller IP core supporting a maximum throughput of 5.8 Gbps with M-PHY HS-G3 single lane, or 11.6 Gbps with M-PHY HS-Gear 3 2-lane operation, meeting the greater data transfer rates and lower power requirements of advanced mobile applications such as smartphone and tablets.

NetSpeed released a major update to its fully configurable cache-coherent network-on-chip IP. The latest version implements an optimized last-level cache and an accelerator for I/O-coherent traffic.


Siemens will use technology from NXP and Cohda Wireless for secure communication of vehicles with surrounding traffic infrastructure in various field tests and pilot projects, including the A58 motorway in the Netherlands, A9 motorway in Germany, and the Living Lab in Austria.

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