The Week In Review: Design/IoT

Aldec acceleration software; IC packaging for WLCSP; Imagination restructuring update; TSMC certifications.



Aldec updated its emulation and simulation acceleration software package for high speed prototyping boards, adding a SCE-MI Pipes-based flow for streaming large amounts of data, and a 30% speed increase for all emulation modes. Plus, Aldec’s mixed-language FPGA design and simulation platform now includes a complete coverage analysis package for FPGA and ASIC designers with the addition of Condition and Path Coverage to its ACDB coverage database.

Cadence unveiled a complete IC packaging design and analysis solution for advanced Fan-Out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs. The set of tools includes multi-substrate interconnect pathway design, refinement, implementation and manufacturing verification and signoff spanning die I/O pad rings through IC package to system PCB.


Rambus licensed technologies designed to protect against DPA and other side-channel attacks to Altis Semiconductor. The agreement extends to software developed by Altis customers when executed on certain Altis manufactured chips.

eSilicon won a deal with indie Semiconductor, which utilized eSilicon’s online STAR platform for both a multi-project wafer prototype and a full-production GDSII handoff of indie’s Lodestar chip to facilitate power delivery in new USB-C cables.

Cadence collaborated with Mellanox Technologies to demonstrate multi-lane interoperability between Mellanox’s PHY IP for PCIe 4.0 technology and Cadence’s 16Gbps multi-link and multi-protocol PHY IP implemented in TSMC’s 16nm FinFET Plus process.

NXP launched a new SDK for Kinetis microcontrollers to support home automation applications using Apple’s iOS framework HomeKit. Plus, OrCam selected NXP’s i.MX 7 series applications processor to power its new wearable personal assistant device.


Imagination ramped up its restructuring program, and will divest or shut down non-core and/or cash consuming units as well as further reduce overheads. Businesses that are being divested include those primarily aligned with the consumer radio business in the past, and the SoC design business will be refocused and rescaled. As part of the cost-cutting measures, Imagination will reduce its headcount by 200 people in addition to the 150 people from the first restructuring announcement. The company has no planned reductions in its graphics and multimedia, MIPS, and connectivity businesses.

TSMC Certifications

A raft of companies received certification for TSMC’s 10nm FinFET process as well as early design starts on its 7nm FinFET process, including Ansys, Cadence, Mentor, and Synopsys. Additionally, tools from Ansys, Cadence, and Mentor are available for TSMC’s Integrated Fanout (InFO) wafer-level packaging technology for 3D ICs.

ARM and TSMC will team up on a 7nm FinFET process technology which includes a design solution for future low-power, high-performance compute SoCs. The agreement extends previous collaborations on 16nm and 10nm FinFET that have featured ARM Artisan foundation Physical IP.

Cadence is updating its high-speed SerDes communication interfaces and low-latency DDR IP to support TSMC’s 16nm FinFET Compact (16FFC) and 28nm HPC Plus (28HPC+) process technologies. Synopsys also announced a broad IP portfolio for the 16FFC process. eMemory’s OTP technology NeoFuse has been verified for 16FFC as well.

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