Thermal Analysis Of 3D Stacking And BEOL Technologies

Thermal challenges in 3D-IC designs can cause a significant risk in meeting performance specifications. While the pace of Moore’s Law has slowed in recent years, system technology co-optimization (STCO) promises to mitigate technology scaling bottlenecks with system architecture tuning based on emerging technology offerings, including 3D technology.

AI-driven inference accelerators continue to expand the 2D system-on-chip (SoC) footprint, primarily supporting increased compute and memory requirements. This, in turn, results in routing congestion, which degrades system-level power, performance, and area (PPA). 3D-IC technology is a solution that interconnects back-end-of-line (BEOL) bottlenecks, offering significant PPA benefits enabled with fine pitch 3D interconnect and fine grain functional partitioning. 3D-ICs increase on-chip bandwidth, which reduces latency and footprint to improve integration yield and cost reductions.

Power density continues to exceed the cooling capabilities, especially for high-performance computing (HPC) systems. The presence of the 3D interface layer, which enables signal and power transmission between different dies, contributes to higher thermal resistance (Rth), increasing the severity of the thermal wall. The practical values of Rth vary for different 3D stacking technologies and depend on the materials used for dielectric and 3D structures. Consequently, more sophisticated cooling systems are required.

Cadence, imec, and Université Libre de Bruxelles have co-written a detailed white paper, “Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoCs,” which analyzes the impact of material properties of embedded micro-bumps (EμBumps) and wafer-to-wafer hybrid bonding (W2WHB) on the thermal behavior of the package stack in 3D-ICs.

The paper presents a thermal analysis of advanced complementary metal oxide semiconductor (CMOS) BEOL and 3D interface layers for different 3D technology and cross-section assumptions, 3D stacking configurations, and system-level partitioning scenarios. Specifically, it focuses on embedded EμBumps and wafer-to-wafer hybrid bonding (W2W HB) 3D stacking technologies, studying the impact of metal density in the 3D interface layer on the thermal behavior of the stack. It explores the impact of 3D partitioning scenarios on the maximum temperature in the stack by comparing the memory-on-logic (MoL), logic-on-memory (LoM), and logic-on-logic (LoL) in 2-die 3D-ICs, as well as 3-die stacks in memory-on-memory-on-logic (MoMoL) configurations.

Methodology and experimental setup

This study utilizes MemPool, a highly configurable, multi-core SoC architecture for embedded and general-purpose AI applications. The SoC instance with 64-RISC-V cores and 512KB L1 and 2MB L2 cache memories was implemented as a 2D- and 3D-IC to derive PPA parameters before thermal analysis. The 2D process design kit (PDK) is based on an imec A14 nanosheet device, with 13 metal layers frontside BEOL, a buried power rail (BPR), and three backside metal layers. Electrical properties were characterized assuming 0.7 V and 25◦C. Timing and geometry views of the memories were generated using an in-house memory compiler, assuming layouts from a single static random-access memory (SRAM) cell for simulating a complete SRAM subarray.

Physical implementation was performed using Cadence Genus Synthesis Solution for logic synthesis, Innovus Implementation System, and Integrity 3D-IC Platform for 2D and 3D implementation, respectively. Voltus IC Power Integrity Solution and Celsius Thermal Solver were used for power and thermal simulations.

The impact of 3D integration versus 2D on the thermal profile in the package was compared. Figure 1 shows the complete package with cooling and PCB (left), chip layers for 2D and 2-dies 3D-IC with FS-PDN and BS-PDN (middle), and chip layers for 3-dies 3D-IC (right) (schematic only, not to scale).

Fig. 1: Complete package with cooling and PCB (left), chip layers for 2D and 2-dies 3D-IC with FS-PDN and BS-PDN (middle), and chip layers for 3-dies 3D-IC (right) (schematic only, not to scale).

Conclusion

The paper describes the analysis of the impact of different 3D integration technology parameters, partitioning scenarios, 3D stacking options, and power delivery approaches on the temperature profile in the layer stack. Studies were performed on a 64-core SoC with L1 and L2 memories and power density like HPC applications.

Fig. 2: The Tmax in the chip layer(s) and Rth for increasing the amount of metal density in the 3D interface layer for EμBumps and W2WHB.

It was shown that at 20% of metal density (or more) in the 3D interface layer, the Tmax is dominated by the BEOL; hence, the choice of 3D interface technology (EμBumps or W2WHB) does not have a thermal impact. Figure 2 shows the Tmax in the chip layer(s) and Rth for increasing the amount of metal density in the 3D interface layer for EμBumps and W2WHB.