Time For New Rules

Is Moore’s Law dead? Brigadier General Paul Fredenburgh, commandant of the Dwight D. Eisenhower School for National Security and Resource Strategy, asked that question to four industry CEOs last week while visiting Silicon Valley with some of his students. He received four highly nuanced, if not different, answers.

Left to right: Lip-Bu Tan, Cadence; Wally Rhines, Mentor Graphics; Simon Segars, ARM; Aart de Geus, Synopsys. Photo courtesy of ESD Alliance.

From one perspective or another, all of the CEOs were all correct. It’s taking longer to move from one process node to the next, but there is significantly more compute power being offered at each new node. While that isn’t technically a doubling of transistors every two years or so, performance continues to increase an average of 30% every couple of years, either through architectural changes, new materials or different packaging approaches.

Moreover, there is no end in sight to how long this will continue. 2.5D, fan-out wafer-level packaging and full 3D will radically improve performance and lower power. While it’s not clear the price per transistor will decrease every couple years, there definitely will be economies of scale as these new approaches see more mainstream applications.

What is becoming obvious, though, is that Moore’s Law as it was originally written is getting tougher to follow. There are several reasons for this:

1. Quality is becoming a bigger issue as semiconductors begin making inroads in safety-critical and industrial markets, including autonomous vehicles, robotics and personalized medicine. In the past, systems companies figured that if they had a problem, they could fix it in the next rev of a chip and it wouldn’t persist beyond the next node. That works for consumer electronics or mobile devices, but chips used in safety-critical and industrial markets are expected to last a decade or more. Quality takes on a whole new meaning in those markets. It requires simulation models for how devices will perform over time (reliability), a combination of predictive analytics and post-production data mining to determine what errors slipped through and how that happened. It also requires much more extensive testing than what has been done in the past.
2. Market demand for moving to the next process node will continue, but the number of high-volume markets is shrinking. Companies such as Samsung, Intel and Xilinx all need increased transistor density. But for other companies, density isn’t the only way to solve their power/performance/cost issues. In fact, shrinking features is no guarantee of increased performance in the context of increasing RC delay, growing contention for memory and I/O resources, thermal dissipation, and a host of other factors that begin showing up at the most advanced nodes.
3. Despite the fact that EUV is moving forward after years of delays, the big challenge with advanced nodes is time. EUV will help. But that’s only one piece of the puzzle. It takes longer to design chips at advanced nodes because design teams now have to worry about power and throughput, and it takes far longer to verify designs because they have more power domains, signal integrity issues, and more functionality to take into account. It also takes more time to integrate IP from a variety of sources, to create photomasks, to complete various manufacturing steps such as deposition and etch, and ultimately to test these chips.

While Moore’s Law is continuing in one way, it also has ended in another. And while collectively this is referred to as Moore’s Law, it bears only glimmers of resemblance to the observation first penned by Gordon Moore. In fact, it it’s time for the semiconductor industry to come up with a new term. A group of determined engineers can make any shape peg to fit in any shape hole with maximum efficiency, but it gets harder when the shapes are changing on both sides.