Too Many Rules

By Ed Sperling
The number of restrictive design rules that have to be dealt with by routers at 28nm and beyond has increased by several orders of magnitude compared with several generations ago, creating havoc in the automated tools world and slowing down the entire design process.

At a time when market windows are shrinking, complexity is making it harder to meet even the old schedules. That has prompted everything from new design strategies that incorporate more third-party IP and full subsystems to changes in how long companies stay at one process node and whether they skip nodes. In some cases, it also has led to shrinking the verification schedules, which raise questions about just how bug-free chips will be in the future, and how much can be accomplished once chips hit the market through software updates.

Particularly hard hit are the routers. Routers are a key part of any design. Place and route has automated much of this complex but highly redundant task for decades, only to be pushed back into redressing the issue at each successive node. Something has changed over the past couple nodes, though. There is more to consider, and routers are paying the price. Because wires don’t scale as well as transistors, the resistance causes heat and noise that can interrupt signals. That has to be taken into account by the router.

Add to that more metal layers, more and increasingly complex interconnects, and more congestion around memories that are scattered throughout SoCs and the problem of routing becomes even tougher. There has been much work done to solve this problem, one node at a time. But EDA vendors say there is much more to be done at each new node, making the problem worse.

“Yesterday’s routers were overworked, too,” said Aart de Geus, chairman and co-CEO of Synopsys. “But the advances being made are remarkable.”

Whether those advances are sufficient, though, is a matter of debate, particularly at 28nm and beyond. Throw in double patterning at 20nm, and finFETs at 14nm, and it’s enough to create panic in some circles.

“With double patterning and triple patterning, all the EDA guys say everything is ready—and it’s true that most of the pieces are ready—but not everything can be combined,” said Jean-Marie Brunet, product marketing director for litho-friendly design and DFM at Mentor Graphics. “You need to change how you deal with place and route in double patterning. It impacts the router, the placer, how you create router fill and pin access.”

Brunet said there are now about 2,000 to 2,500 rules for the router to deal with. And he said almost every major EDA player’s router does basically the same thing, so if one vendor is wrestling with the problem then so is everyone else.

“It’s no longer just layout that is very complicated. The problem is that the router has to understand the rules and still do all the things that it has been doing. The complexity of vias is unbelievable. At 14nm we’re seeing double vias everywhere, while at 28nm we did not have double vias. And how do you explain to a router that a via is rectangular?”

Rectangular vias were introduced by the major foundries at 28nm. It is uncertain at this point whether they will be replaced by cylindrical vias in the future, but it’s clear this has made routing more difficult. More complexity equals more design rules.

“We used to have 10 pages of design rules 20 years ago,” said Mark Bohr, senior fellow of the technology and manufacturing group at Intel. “It’s now more than 100 pages, and that puts a huge burden on automated layout and routing. You need to work on the tools a couple years in advance.”

From a design standpoint, each new node requires more restrictive design rules just to make sure that chips are functional and that yield is sufficient. But adding 3D transistors and double patterning require another big jump in the number of design rules. Bohr, who is working on the 10nm node, said Intel is now in the early development phase of defining design rules for that node.

“This is the price we pay to expand 193nm immersion lithography,” he said. “The good news is that we can re-use some of the tools. The bad news is that it requires a lot more rules.”

GlobalFoundries is working on 10nm place and route tools, as well, according to CTO Gregg Bartlett. “This requires a lot of collaboration across the ecosystem,” he said. “We’re in early discussions on this.”

Going up
One of the ways that chipmakers have dealt with this kind of complexity has been to add more metal layers. This is a sort of crude stacked die approach, rather than one using through-silicon vias and separate die or subsystems, but it brings its own unique brand of problems from a design standpoint.

“There are two challenges as far as the router goes,” said Rob Aitken, an ARM fellow. “The first involves metal layer one rules, which need to have bi-directionality—vertical and horizontal. Then there is everything else. But a huge amount of the complexity in the rules is the interaction of the vertical and the horizontal. That can bring it to its knees.”

And increasingly it has. The amount of time spent on the routing side of the design is increasing, which is part of the reason there has been such slow movement to the next process node. It’s also one of the reasons there has been such an explosion recently in the design for manufacturing software market, which serves as yet another checkpoint for rules violations.

FinFETs will add yet another volume of design rules, which is one of the reasons that fully depleted silicon on insulator (FD-SOI) has gained more attention lately. The rules are basically the same, making it an attractive alternative all the way down to 14nm. After that, it is likely that both finFETs and FD-SOI will be required.

“The big question is what is the turnaround of the routing capability,” said Mentor’s Brunet. “One way you get around that is to turn off all the features when you test it, so it looks good when you bring a product to market. But that doesn’t work for long. And improving layout at the end of the design cycle is difficult.”