Trends In Testing: New Challenges Create New Opportunities

As advancements in semiconductors and microelectronics soldier ahead into emerging, even uncharted, territory, new test challenges arise. To that end, let’s look at a few key trends and challenges that are driving opportunities for innovation in the test sector.

Technology convergence has been a buzzword for some time, and this trend is only going to intensify with the heightened need to move, access, and analyze massive volumes of data. As a result, data analytics technologies (Big Data, artificial intelligence [AI], and machine learning) will continue to play a vital role in driving test efficiencies – not just operational, e.g., improving overall equipment efficiency (OEE), but also transformational: enabling data to feed forward and backward between test insertions, as well as outside of test. The reality is that the lines are blurring between the front and back ends of test, and the insertion points change, depending on device type and lifecycle status. So, the test flows that happen throughout the lifecycle of the device need to be flexible.

Complex high-performance computing (HPC) and AI devices are growing very large, and because of interposers and bridging, their power requirements can exceed 1000W. This means that we need to be able to manage temperature with a high degree of precision during testing. These large devices also require additional compute and analytics capability during test. To this end, we developed our ACS Edge solution, which essentially adds a supercomputer alongside the tester to open up compute power and start to enable real-time adaptive test.

With these developments, the system will become enormously complex, requiring verification of entire systems (hardware, firmware/embedded applications, and software). This means we’ll be seeing a broader deployment of system-level testing (SLT) for both systems and modules, as well as SLT/ATE at the probe level for known good die, including active thermal management solutions. To this end, we’ve incorporated into our offerings the test-related accessories we acquired upon purchasing Essai, including sockets, thermal control units, and other test subassemblies. Our value proposition rests in our ability to address the full hardware stack and in the comprehensive nature of our offerings.

In the broader test arena, generation, validation, and optimization of required test content such as scan vectors, built-in self-test (BIST), and functional test (software code) will need massive support and cooperation between the EDA and ATE industries. Advantest has established strong relationships with the leading EDA providers to help drive these efforts. The industry is also going back and mixing functional tests more with structural tests, and more design-for-test (DFT) techniques are being added. While increased scan, serial high-speed scan over USB, and PCIe ports are being used, that still isn’t enough, which brings us back to SLT continuing to be deployed.

For 5G, test solutions are largely in place. Some high-volume manufacturing (HVM) device interfacing/interconnect technologies like over-the-air (OTA) are coming along, while test development is starting for advanced millimeter-wave (i.e., THz, 6G). There will also more use of on-chip sensors and agents to monitor device performance all the way through the fab, assembly and in-field. This traceability is vital to ensuring ATE plays a critical role in pulling data from sensors – this heightened need for data extraction and analysis is a recurring theme that permeates everything going forward.

Continued electrification of cars will also drive lots of growth in test, including challenging areas like high voltages – i.e., those greater than 1kV – which require different kinds of methodologies. These higher voltage requirements are also needed for silicon carbide (SiC) applications in vehicles. SiC, like gallium nitride (GaN), has been around for a long time and is finding new life in applications such as battery management. We can cover this with our mixed-signal configurations and our integrated power solutions.

With respect to packaging, we expect to see a bifurcation in the industry: HPC/AI will move to 2.5/3D ICs, while mobile will remain on monolithic 2D for a little while longer. We’re already into 2.5 and 3D, and we have been for some time. However, with hybrid bonding and die stacking, we’re moving into 3D IC. When that is fully implemented, it will bring some tough new challenges. We believe a holistic approach is required to create high-power solutions that will then be coupled with other chips in a package.

In addition, there will be new approaches to address the “memory wall,” such as large eRAMs, 3D stacked RAMs, co-packaging on 2.5D, or access via serial I/O. Power consumption of I/Os may also drive the integration of optical I/O. The first step will be co-packaged optics (CPO), which involves heterogeneous integration of optics and silicon on a single packaged substrate aimed at addressing next-generation bandwidth and power challenges.

As you can see, many technology trends have test requirements that overlap or coincide, with demands created by massive amounts of data generation and processing playing a massive role. Testing at the exascale level requires powerful equipment that can handle the challenge. We are meeting this challenge with our EXA Scale test system, built on our flagship V93000 architecture, which addresses the challenges of very high scan-data volumes, extreme power requirements, fast yield-learning and high-multisite configurations.