TSMC Tech Symposium 2025

TSMC held its North America Technology Symposium on Wednesday, April 23, 2025 at the Santa Clara Convention Center and presented update information on its relentless march to ever finer geometries and higher levels of scaling.

Figure 1, below, shows TSMC’s latest advanced technology roadmap. Compared to the roadmap presented at last year’s tech symposium, the new roadmap shows the “High-end” segment change of N2X moving out into 2027 and the new addition of A14 in 2028.

Fig. 1: Advanced Technology Roadmap

For the “Mainstream” segment, the new slide shows N3C appearing in 2026, which may have been the plan all along.

N3 is being billed as the “Last and Best FinFET Technology.” TSMC stated that N3E is already in high volume production for mobile and HPC/AI products with excellent yield. N3P entered volume production in the last quarter of 2024 and is slated to succeed N3E. Multiple variants of N3 are being offered to address application specific needs with N3X targeted for client CPU, N3A for automotive and N3C for “value-tier” products and it will offer a cost reduction for customers.

TSMC provided PPA comparison information for N2P, A16, and the newly announced A14. The tables in Figure 2 below show the improvements relative to previous nodes. Typically, logic density scales better than the overall chip density so it’s notable that the A14 chip density improvement over N2 is relatively close to the logic density improvement.

Fig. 2. Advance Node PPA Comparisons.

N2 has received multiple tape outs and remains on track for production in the second half of 2025. This is the first post-FinFET node using TSMC’s Nanosheet technology and the device performance is close to target. N2P is on track for production in the second half of 2026 and N2X will offer an additional ~10% Fmax for 2027.

A16 Nanosheet will include TSMC’s Super Power Rail (SPR) for backside power delivery and is on track for production in the second half of 2026.

A14 features the 2^nd generation of the nanosheet transistor and continuous pitch scaling. Currently, the development progress is very good with yields ahead of plan and device performance on track. A14 production is targeted for 2028 with the SPR version planned for 2029.

Figures 3, 4, and 5 below show historical data for the percentage of wafer revenue for each technology node going back 18 years in Figure 3 and focusing on the previous 7 years in Figure 4 to provide a closer look at the introduction of 7nm and below nodes.

Fig. 3: Percent Wafer Revenue by Node Per Calendar Quarter (18 Years).

Fig. 4: Percent Wafer Revenue by Node Per Calendar Quarter (6 Years).

Fig. 5: Percent Wafer Revenue for <= 7nm by Calendar Quarter.

As shown in Figure 5 above, the 7nm and below FinFET nodes now account for almost three-quarters of TSMC’s wafer revenue. In other words, the technologies introduced in the last 7 years account for over 70 percent of TSMC’s wafer revenue today.

The Nanosheet family of technologies will be introduced during the remainder of this decade and the adoption rate of N2 is already far outpacing N5 and N3. Figure 6 below shows how customer adoption continues to expand going forward.

Fig. 6: N2 Customer Adoption Rate in Terms of Tape-Outs.

The adoption of new nodes after N5 has accelerated. 1^st year tape outs for N2 are at 2x N5 and 2^nd year tape outs have grown to 4x of N5.

Looking beyond Nanosheet TSMC is projecting complementary field-effect transistor (CFET) next, a 3D architecture where n-type and p-type transistors are vertically stacked, to possibly be followed by 2D transition metal dichalcogenides (TMD) or carbon nanotube (CNT) devices. TSMC has a website with industry outlook and new technology information and information presented at IEDM 2024 here.

Figure 7 below shows TSMC’s integrated power delivery solution. With chips exceeding the 1KW barrier, the current necessary for these parts exceeds 1000 Amperes and getting good clean power delivery to the various components that make up these systems is a challenge. Additional capacitance is required, and the diagram shows deep trench capacitance (DTC) added above the interposer as well as embedded (eDTC) in the interposer.  (Readers may remember an article, Managing Voltage Variation, where we looked at Graphcore’s use of DTC to get dynamic voltage drop under control.) In addition, there’s also the capability of on-wafer inductors for integrating power management integrated circuits (PMIC). These will be quite useful for the development of complex and energy hungry systems targeted for HPC and AI applications.

Fig. 7: Integrated power delivery solutions.