Ultra-Small Fan-Out Packaging Solution

With the advent of the Internet and multimedia, electronics miniaturization in the form of integrated circuits has become an indispensable part of our lives. To ensure its long-term operation and reliability, the rapid development of integrated circuits depends on advancements in not only the design and manufacturing of chips, but also its packaging.

As the market demand for consumer and communication electronics continues to grow, fan-out packaging has become increasingly favored by the market in recent years. Fan-out packaging maintains the small size and lightweight advantage of WLCSP whilst ensuring its good electrical and thermal conductance. At the same time, the wiring and pins extend beyond the chip for greater design flexibility and the molding material on the sides and bottom walls of the chip provides effective operational protections subsequently and improved reliability.

Fan-out packaging needs to be reconstituted through wafers, during which the chip needs to be placed in the set position. However, the position at which the chip is placed on often deviates from the set position because of the slight inaccuracies by the placement machines and the thermal pressures between the molding material and the chip. This offset affects the subsequent lithography alignment and RDL routing. Furthermore, the subsequent production of reconstituted wafers involves molding material, chips, insulating layers, and metal layers, which are made of different materials, the expansion with heat and contraction with cold of these materials may lead to wafer warpage.

When serious, the wafer warpage may even end subsequent processes. These aforementioned concerns underlie important considerations when designing the packaging, especially for small chip fan-out packaging. During the wafer reconstitution process, offset in the position can occur because of the weak and lack of effective area for bonding, and the warpage problem can reduce the traditional packaging fan-out ratio (package size/chip size) and effective area. Such offsets are also more severe in multi-chip situations. Therefore, making the design small-sized with a large fan-out ratio via the traditional fan-out packaging process remains a challenge.

To address these issues and increase the handiness and flexibility of the packaging design, ECP (Encapsulated Chip Package) technology has been introduced. ECP technology is an advanced chip-first and face-down packaging process, unlike other packaging processes that use wafer reconstitution molding compounds. The ECP process uses a laminating molding film instead of the conventional liquid or powder molding compound. In addition, the lamination process replaces the wafer molding process for ultra-thin packaging of the chips. The lamination process allows the reconstituted wafers to achieve a high degree of flatness and avoid cavities in the wafers. Additionally, as opposed to using liquid or powder compounds as the wafer molding, it can also effectively reduce the chip offset problem and achieve small-size, large fan-out ratio packaging.

In addition, thanks to the unique process of ECP and the low modulus characteristics of the lamination film, the silicon support on the backside of the reconstituted wafer can effectively reduce its warpage and overcome the warpage related problems.

ECP technology allows for not only fan-out, single-chip and multi-chip packaging, but also ensures five-sided package protection. It has a small size and large fan-out ratio, and can effectively overcome the wafer warpage problem.

Advantages of ECP packaging technology
With the ECP packaging technology, the incoming chip is first thinned and then divided into a single chip. With the chip facing down, it is placed on the carrier silicon attached to the double-sided film via a pick-and-place bonding process. The chip is then covered with a lamination molding film to achieve five-sided protection of the chip. Following this, the silicon wafers need to be supported by bonding to the backside of the lamination film. Lastly, the carrier – silicon wafer is removed to obtain the reconstituted chip. Upon completing the RDL routing and bumping processes, the final package form is obtained by grinding. The bonded wafer supports throughout the manufacturing process until grinding, when the support silicon wafer can be selectively removed from the packaging. Figure 1 shows the incoming chip and the final Fan-Out ECP process packaging.

Fig. 1: Fan-out ECP incoming chip and final package.

ECP processing can eventually achieve an ultra-thin five-sided package with a thickness of 200 μm without exposing the chip. Furthermore, the backside of the packaging body bonding to the supporting silicon can also effectively improve the bending strength and mechanical heat dissipation. ECP technology enhances the WLCSP fan-in packaging to achieve the smallest portable packaging size at the lowest production and testing costs and is used mainly in products with small I/O pin counts. The sidewalls and bottom are protected by the molding, effectively protecting the package from mechanical stress and external environmental changes.

Fig. 2: Fan-out ECP packaging.

ECP packaging applications
ECP technology is mainly used in applications such as integrated packaging, light shielding, mechanical protection and reliability enhancement, small size packaging and multi-chip packaging. In particular, single-chip Fan-out packaging technology effectively reduces costs.

As shown in Figure 3, the chip size in the WLCSP package needs to be 0.8mm x 0.8mm due to limitations of the number of I/O and minimum pitch of pins required. However, while meeting the number and spacing of the package pins, the chip size designed by the Fan-Out ECP packaging technology can be further reduced to 0.55mm x 0.47mm. The number of chips on each silicon wafer also at least doubles. Compared to WLCSP, ECP can effectively reduce the customer’s overall costs.

Fig. 3: Small size WLCSP versus fan-out ECP packaging.

The laminating material around the chips plays a mechanical protection role, preventing them from fragmenting in the subsequent transferring processes. The small size of the Fan-Out ECP package is an added advantage in this application.

Figure 4 is an RF module package implemented by Fan-Out ECP technology, integrating different numbers of chips of various functions into a single package. This establishes the circuit connection in the chip and prepares the package for systemic functions.

Fig. 4: Multi-chips fan-out ECP packaging

Following ECP packaging technology, JCET also delved into the multi-dimensional fan-out integrated technology XDFOI (X-Dimensional Fan-out Integration, XDFOI). XDFOI adopts a 2.5D TSV-less technology, where the minimum RDL line width/space distance can reach 2um/2um and accommodate multi RDL layers to achieve various 2D, 2.5D or 3D heterogeneous packages. Compared to the 2.5D TSV packages, it allows for more flexible structural designs with better performance and reliability at a lower cost. It is a package solution for high-end products like FPGA, CPU, GPU, ASIC, APU, AI, networking communications, and 5G communication chips, as well as for chiplets and Heterogeneous Integration Packages (HIP).

Fig. 5: Multi-chips XDFOI packaging.

Looking to the future, as the IC industry continues to grow, JCET Group will continue to develop new technologies, optimize its products, and constantly expand its innovation and service capacity.