Understanding Optical Inspection For CIS

The demand for smartphone cameras, video conferencing, surveillance and autonomous driving has fueled explosive growth of CMOS image sensor (CIS) manufacturing in the last decade. While CIS becomes an increasingly important element in the production of today’s consumer electronics, there are unique challenges in production that must be addressed. As pixel sizes shrink, we see an inverse relationship with the number of pixels in the array increasing, which presents challenges for process control of the sensor, especially as it relates to the color filter array (CFA) and on-chip lens (OCL). With the push to 1µm and below pixel sizes, the ability to find sub-micron defects and macro-level variations within the pixel array is even more important to ensure uniform and unobstructed responses throughout the active pixel sensor array (APS).

CIS is unique from other semiconductor devices because it converts light energy into electrical signals. It is manufactured on silicon wafers similar to semiconductors and follows typical back-end packaging processes such as grinding, sawing, and electrical testing. A typical CIS device has an ASP region in the center of the die with electrical I/Os (bondpads) on the periphery. Deionized water is often used to clean up mobile contamination left behind during the wafer thinning or die singulation process which has an inherent risk of staining or leaving a residue on the APS that affects the quantization of light and is considered a killer or yield limiting defect.

The CIS device manufacturing process resembles typical semiconductor devices, except that in a color image sensor a CFA and OCL process is added for the photodiodes or pixels in the APS to produce a color image.

Typical back-end packaging steps for CIS.

Defects created during the color filter deposition step are sensitive to different wavelengths of illumination. Defects from the red filter deposition are sensitive to red illumination and defects from the green filter deposition are sensitive to green illumination.

An APS, by its design, is intended to absorb as much light as possible. This light absorbing nature makes visual inspection very difficult due to the fact that visual inspection relies on reflected light to produce an image. An APS looks extremely dark under normal bright field illumination and defects such as water stains or film variation are not visible. Even if these defects were visible under bright field illumination, such defects on the APS have very low contrast from the background and the traditional image comparison detection method cannot find such low contrast defects.

Another yield limiting defect for CIS wafers is photoresist (PR) coating thickness variations. PR thickness variations on APS can affect the image sensor performance. Water stains or slight variations of the PR coating thickness are not critical defects for most types of semiconductor devices, but they are critical defects for CIS as they can affect pixel level response to light. Two common types of PR thickness variations found on CIS wafers are shown below. Both types of PR variations can cause uneven pixel level light response within the same die. As 300mm wafers become the dominant base for CIS manufacturing, keeping the PR coating uniform on a larger area adds process challenges.

Two common types of PR thickness variations found on CIS wafers.

Electrical testing for CIS is also different from typical semiconductor devices in the sense that the input is light. Light shines on the dies during electrical testing and CIS dies convert that light energy into electrical voltages. A tester reads the electrical output from the CIS dies, converts the results into an image format, and any kind of pixel level variation visible to the human eye can be detected at the electrical test stage. However, any kind of defects added after electrical testing, such as water stains or cracks during sawing, need to be detected via visual inspection. This is the primary reason why CIS dies are delivered to the camera module assemblers in a re-constructed wafer format with final visual inspection to detect the defective dies. Detecting the defective dies at the final visual inspection will avoid any usage of defective chips from the assembly of the camera module and save costs.

As CIS technology improves, the dies are becoming larger, pixel sizes are shrinking and the challenges to keep the process under control to achieve the maximum yield drives the need for CIS inspection.