Reliability At 5nm And Below


The best way to figure out how a chip or package will age is to bake it in an oven, heat it in a pressure cooker, and stick it in a freezer. Those are all standard methods to accelerate physical effects and the effects of aging, but it's not clear they will continue working as chips shrink to 5nm and 3nm, or as they are included in multi-die packages. Extending any of those kitchen-like appr... » read more

The 3 Main Obstacles To Zero DPPM And How To Overcome Them


As we all well know, there are multiple mission critical applications in today’s “Age of Smart,” that are calling for zero DPPM (defective parts per million) in semiconductors and electronic systems. In industries such as automotive, medical, aerospace, and more, where lives are at stake, defective parts are not an option. The quality imperative However, with the ever-growing complexity o... » read more

Challenges Grow For Finding Chip Defects


Several equipment makers are developing or ramping up a new class of wafer inspection systems that address the challenges in finding defects in advanced chips. At each node, the feature sizes of the chips are becoming smaller, while the defects are harder to find. Defects are unwanted deviations in chips, which impact yield and performance. The new inspection systems promise to address the c... » read more

Inspection, Metrology Challenges Grow For SiC


Inspection and metrology are becoming more critical in the silicon carbide (SiC) industry amid a pressing need to find problematic defects in current and future SiC devices. Finding defects always has been a challenging task for SiC devices. But it’s becoming more imperative to find killer defects and reduce them as SiC device vendors begin to expand their production for the next wave of a... » read more

Challenges And Solutions For Silicon Wafer Bevel Defects During 3D NAND Flash Manufacturing


As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer center and the wafer edge. Industry participants are working to reduce defect density at the wafer edge to improve overall wafer yield. Attention has focused on common wafer bevel defects s... » read more

New Imaging Tech Finds Buried Defects


By Shinsuke Mizuno and Vadim Kuchik Defects and contamination on the wafer can slow process development times and limit performance and yield. As chips get more complex, more defects can become buried within the increasing number of layers in the design. Finding and analyzing these buried defects is a major challenge for the industry, especially during the early learning cycles of new manufa... » read more

Breakthrough For Scan Diagnosis With Machine Learning


Cell-aware diagnosis is a new and effective way to detect defects inside standard cells. Industry standard failure analysis (FA) results from a major foundry show that cell-aware diagnosis is very effective at increasing the resolution of the diagnosis by reducing the number of suspects in cell-internal defect data. With advanced technology nodes, we have more complex layout structures and f... » read more

Gaps Emerge In Automotive Test


Demands by automakers for zero defects over 18 years are colliding with real-world limitations of testing complex circuitry and interactions, and they are exposing a fundamental disconnect between mechanical and electronic expectations that could be very expensive to fix. This is especially apparent at leading-edge nodes, where much of the logic is being developed for AI systems and image se... » read more

Making AI More Dependable


Ira Leventhal, vice president of Advantest’s new concept product initiative, looks at why AI has taken so long to get going, what role it will play in improving the reliability of all chips, and how to use AI to improve the reliability of AI chips themselves. » read more

E-Beam Review And CD Measurement Revolutionizes Display Yield Management


Fundamental changes are occurring in the display industry, driven by demands for higher-resolution screens and other capabilities for both mobile and TV applications. To meet these demands, the display technology roadmap in this article calls for innovations in materials, processes and device technology. Critical requirements include smaller design rules and the adoption of a range of materi... » read more

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