Things That Go Bump In The Daytime


There is no argument that autonomous technology is better at certain things than systems controlled by people. A computer-guided system has only one mission — to stay on the road, avoid object, and reach the end destination. It doesn't get tired, text, or look out the window. And it can park within a millimeter of a wall or another vehicle without hitting it, and do that every time — as lon... » read more

Making 3D Structures And Packages More Reliable


The move to smaller vertical structures and complex packaging schemes is straining existing testing approaches, particularly in heterogeneous combinations on a single chip and in multi-die packages. The complexity of these devices has exploded with the slowdown in scaling, as chipmakers turn to architectural solutions and new transistor structures rather than just relying on shrinking featur... » read more

Extreme Quality Semiconductor Manufacturing, Part 1: Automotive


By Ben Tsai and Cathy Perry Sullivan Across the full range of semiconductor device types and design nodes, there is a drive to produce chips with significantly higher quality. Automotive, IoT and other industrial applications require chips that achieve very high reliability over a long period of time, and some of these chips must maintain reliable performance while operating in an environmen... » read more

Scan Diagnosis


Jayant D’Souza, product manager at Mentor, a Siemens Business, explains the difference between scan test and scan diagnosis, what causes values in a scan test to change, how this can be used to hone in on the actual cause of a failure in a design, and how to utilize test hardware more efficiently. » read more

Finding Defects In IC Packages


Several equipment makers are ramping up new inspection equipment to address the growing defect challenges in IC packaging. At one time, finding defects in packaging was relatively straightforward. But as packaging becomes more complex, and as it is used in markets where reliability is critical, finding defects is both more difficult and more important. This has prompted the development of a ... » read more

Reliability At 5nm And Below


The best way to figure out how a chip or package will age is to bake it in an oven, heat it in a pressure cooker, and stick it in a freezer. Those are all standard methods to accelerate physical effects and the effects of aging, but it's not clear they will continue working as chips shrink to 5nm and 3nm, or as they are included in multi-die packages. Extending any of those kitchen-like appr... » read more

The 3 Main Obstacles To Zero DPPM And How To Overcome Them


As we all well know, there are multiple mission critical applications in today’s “Age of Smart,” that are calling for zero DPPM (defective parts per million) in semiconductors and electronic systems. In industries such as automotive, medical, aerospace, and more, where lives are at stake, defective parts are not an option. The quality imperative However, with the ever-growing complexity o... » read more

Challenges Grow For Finding Chip Defects


Several equipment makers are developing or ramping up a new class of wafer inspection systems that address the challenges in finding defects in advanced chips. At each node, the feature sizes of the chips are becoming smaller, while the defects are harder to find. Defects are unwanted deviations in chips, which impact yield and performance. The new inspection systems promise to address the c... » read more

Inspection, Metrology Challenges Grow For SiC


Inspection and metrology are becoming more critical in the silicon carbide (SiC) industry amid a pressing need to find problematic defects in current and future SiC devices. Finding defects always has been a challenging task for SiC devices. But it’s becoming more imperative to find killer defects and reduce them as SiC device vendors begin to expand their production for the next wave of a... » read more

Challenges And Solutions For Silicon Wafer Bevel Defects During 3D NAND Flash Manufacturing


As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer center and the wafer edge. Industry participants are working to reduce defect density at the wafer edge to improve overall wafer yield. Attention has focused on common wafer bevel defects s... » read more

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