tag: defects

Advanced Electrical Test Capability For Better Defect Signature Detection In Advanced Package Development
By Jesse Ko - 12 Aug, 2025 - Comments: 0

As the semiconductor world excitingly explores the potential of new advanced package solutions for their intricate and novel designs, challenges arise from undetected defects caused by the complexity of the designs and the lack of accessibility to the interconnects for testing. This typically results in a long cycle time to achieve yield entitlement. Undetected defects at the development stage ... » read more

Easing The Stress For Package-Level Burn-In
By Laura Peters - 10 Jul, 2025 - Comments: 0

Considered something of a necessary evil, burn-in of IC packages during production does a great job of weeding out latent defects so they don’t turn into failures in the field. But as AI and multi-chiplet packages become more common, and concerns about aging circuitry heighten, shifting stress testing to the wafer level looks increasingly attractive from a quality, throughput, and cost standp... » read more

How To Catch “Disappearing” Latent Defects
By Errol Akomer - 19 Jun, 2025 - Comments: 0

Automotive is demanding more emphasis on chip reliability. By 2020, electronic devices will account for over 35% of the manufacturing cost of an automobile, and by 2030, that number is expected to rise to 50%. Tens of thousands of cars are manufactured each day, with each car using thousands of chips — and if even one of those chips fails in the field it may have disastrous consequences: los... » read more

Can Your ATPG Do This? Cut Defects Escaping Detection With ML
By Alex Burlak - 10 Jun, 2025 - Comments: 0

Chipmakers worldwide consider Automatic Test Pattern Generation (ATPG) their go-to method for achieving high test coverage in production. ATPG generates test patterns designed to detect faults in the silicon and ensures they are applied effectively using the chip’s Design-for-Test (DFT) infrastructure. This combination enhances fault detection while optimizing test efficiency. These patter... » read more

EUV’s Future Looks Even Brighter
By Gregory Haley - 20 Feb, 2025 - Comments: 1

The rapidly increasing demand for advanced-node chips to support everything-AI is putting pressure on the industry's ability to meet demand. The need for cutting-edge semiconductors is accelerating in applications ranging from hyperscale data centers powering large language models to edge AI in smartphones, IoT devices, and autonomous systems. But manufacturing those chips relies heavily on ... » read more

Using AI In Semiconductor Inspection
By Ed Sperling - 05 Feb, 2025 - Comments: 0

AI is exceptionally good at spotting anomalies in semiconductor inspection. The challenge is training different models for different inspection tools and topographies, and knowing which model to use at any particular time. Different textures in backgrounds are difficult for traditional algorithms, for example. But once machine learning models are trained properly, they have proven effective in ... » read more

Cut Defects, Not Yield
By proteanTecs - 14 Jan, 2025 - Comments: 0

Many chipmakers face a difficult trade-off — improve quality without affecting yield. Traditional testing methods fail to navigate this challenge due to their limited visibility below the pass/fail limits, discarding perfectly good chips or letting small defects slip through to the field. The challenge is clear: manufacturers must achieve both quality and yield goals without sacrificing one f... » read more

Achieving Zero Defect Manufacturing Part 3: Prevention Of Defects
By Prasad Bachiraju - 16 Sep, 2024 - Comments: 0

The concept of zero defect manufacturing has been around for decades, arising first in the aerospace and defense industry. Since then, this manufacturing approach has been adopted by the automotive industry, and it has only grown in importance as the sector transitions to electric vehicles. Given the role semiconductors play in today’s vehicles, and will play in the future, it is no surprise ... » read more

Achieving Zero Defect Manufacturing Part 1: Detect & Classify
By Prasad Bachiraju - 11 Jun, 2024 - Comments: 0

Whether the discussion is about smart manufacturing or digital transformation, one of the biggest conversations in the semiconductor industry today centers on the tremendous amount of data fabs collect and how they utilize that data. While chip makers are accumulating petabytes of data across the entire semiconductor process, a question arises: how much of that information is being fully uti... » read more

Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By Design And Process Errors
By James Kim - 22 Feb, 2024 - Comments: 0

Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during any number of process steps. In this article, I want to share a different mechanism that can cause wafer defects. Namely, that these defects can be structural defects that are caused by a biased dep... » read more

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