Unified Power Intent

The next version of the Unified Power Format has been approved, bridging the major differences between UPF/IEEE 1801 and the Common Power Format.

For anyone who works in low-power verification, this is very good news. The new standard is the result of an unprecedented collaboration by chipmakers and EDA companies, and the people who devised a solution to this problem deserve a big pat on the back. They are the unsung heroes of the electronics world, and they have accomplished a complex accord that should make our representatives in government green with envy.

But this also begs the question, “Why were there two standards in the first place?” The blame falls on competitors jumping into the standards battle prematurely, based on the assumption that they could force customers to choose sides with their individual power formats. While it may have seemed black and white enough on paper, it never could have worked outside of a vacuum with a precise set of business conditions, namely winner take all. The reality is that large chipmakers don’t standardize on any single vendor’s tools. They don’t like being locked in, which is why there are still three big EDA vendors and lots of smaller players around the fringes.

While there were crude bridges constructed between these formats—which are the basis of most power verification efforts in complex SoCs—they were hardly perfect. And they were never complete—like bridges that crossed most of the way but never quite reached the other side. New versions of these standards were rolled out to minimize the differences, but that sometimes made the problem even worse. Instead of two standards, engineering teams were forced to contend with multiple versions of each standard and then find a way to tie them all together.

One piece of IP may have been verified with one standard, while another piece of IP was verified with another. And that was true for commercial IP as well as internally developed IP, a problem only made worse by consolidation in the IP business over the past few years.

Unfortunately, that’s still the reality in the semiconductor industry. But when the next version of UPF finally rolls out later this year—version 2.1—chances are good that we finally can put this behind us. And hopefully the EDA industry has learned a lesson about jumping on standards too early and causing their customers grief. Tools are supposed to make the job easier, but in this case tools are being created just to fix other tools. Why does that sound so wrong?

—Ed Sperling