UPF-Driven RTL Power Budgeting For Energy-Efficient Designs

Best practices for using UPF and key questions to consider.

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Energy efficiency of devices has become more critical than ever, with shrinking geometries and increased performance requirements of SoCs in applications ranging from mobile, storage, automotive to processors. Power management, therefore, becomes an important part of IP and SoC design methodology.

While power management is critical in all design stages, an important aspect of this methodology is to ensure the design meets its power specification or power budget as early as possible in the design flow. If the design does not meet its power budget, tradeoffs can be made at the architectural design stage to choose a more power-efficient implementation. Identification of power hotspots and corresponding design changes are easier early in the design flow at Register Transfer Level (RTL) and above than during physical implementation.

Common power management techniques include power gating, multiple voltage islands, dynamic voltage and dynamic frequency scaling. However, existing Hardware Description Languages (HDLs) do not provide a way to capture the power intent of the design. An industry-standard format is necessary to ensure that (a) the power intent of the design can be defined by a power architect in a portable format, (b) the implementation of power management techniques remain consistent throughout the flow, and (c) the design functionality can be verified from RTL through physical implementation.

IEEE 1801 Unified Power Format (UPF) is an industry-standard format for defining the low power design strategies. It is currently available for production use at RTL design abstraction and below, and efforts are underway to extend it to system-level. UPF is portable across vendors and design flows, driving verification and implementation of power intent of the design. A UPF description defines power domains and power distribution network of a design. It also defines the usage and placement of special cells such as retention cells, power switches, isolation cells, level-shifters, etc. in the design. Figure 1 shows an example of power domain architecture and corresponding UPF specification.

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Figure 1: Power domain architecture and UPF example.

While it is essential to perform verification of the design’s power intent, it is also critical to perform early power budgeting. Functional verification ensures that the implemented power management techniques meet the specification and the functionality of the design is not broken during implementation. Similarly, early power analysis ensures that the design power budget is met, and power debug provides guidance to achieve this goal if the initial power target is not met. Following are some questions that need to be asked when formulating the design’s power management strategy:

1. How much power will be saved once the power management techniques are implemented?
2. Will the design meet its power budget once the power specification is implemented?
3. What is the power impact of the special cells that will be added during implementation of retention cells, isolation cells, level shifters, power gating switches, etc.?
4. How good is the coverage of power management techniques? Are there additional hierarchical blocks which could be turned off in certain modes of operation?

A top-down low-power design approach using UPF is effective in analyzing the power consumption of various power architectures before implementation, thereby enabling the identification of the most power-efficient architectures. A quick ‘what-if’ analysis at RTL helps determine the appropriate strategy for saving power. The decision about which power management technique to use will depend upon a number of factors such as design complexity, timing/performance impact, wake-up time, power savings, ROI, etc. Early UPF-driven RTL power budgeting can ensure that the power saved by the chosen power management technique is greater than the power consumed by cells such as isolation cells, retention cells and power switches after implementation. RTL power debug methodology help identify additional hierarchies to shut off during specific modes of operation, leading to power savings beyond the original UPF. Further, a time-based power analysis can enable power profiling of various power domains and power modes.

RTL power tools today can utilize UPF to analyze the design’s power consumption using power management techniques such as power gating. Figure 2 represents the power waveforms for a power gated design using ANSYS PowerArtist. Low power simulations generate power-over-time waveforms without requiring activity files. This further enables quick ‘what-if’ power analysis and refinement of UPF-driven power strategies.

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Figure 2: RTL Power waveform for a power-gated design using UPF.

Designers increasingly are adopting a UPF-driven RTL power budgeting approach as an Ultra-Low Power methodology. It ensures visibility into power savings and enables UPF refinement early in the design flow when there is flexibility to make high impact architectural decisions.



  • Bhaskar

    Good Article with deep insights of UPF standard by PowertArtist for power budgeting.