How STING was used for the functional verification of PULPino RISCY core.
Authors: Shubhodeep Roy Choudhury1, Shajid Thiruvathodi2, Vaidyanathan Seetharaman3, Matt Cockrell4, Jon Michelson5, Jason Redgrave6
Valtrix Technologies Private Limited, Bangalore, INDIA1, 2
Google Inc., Mountain View, USA3,4,5,6
Abstract: — Google uses the PULPino RISC-V core RISCY as a job scheduling and dispatch mechanism for a hardware accelerator (similar to a GPU controller). This requires full compliance with the RISCV RV32I base integer instruction set, standard extensions for integer multiplication and division (‘M’) and compressed instructions (‘C’), and capability to handle interrupts from multiple sources. We used STING, a software-driven verification solution for RISC-V based CPU/SoC implementations, to verify the architectural compliance and functionality of the RISCY core. This verification effort helped uncover 30 RTL, documentation, and toolchain issues in the relatively mature RISCY implementation.
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